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Re: coregen...ip cores????
Well after defining the parameters for your IP core using LOGICORE GUI of Xilinx . a folder with certain files would be made in the directory as specified by u in the start of LOGICORE GUI . In that folder there would be .v file .. open it using notepad++ or with...
If the channel is asyncronous , walsh codes loose their orthogonal properties then why do we use them , we should always use PN sequences , i mean what are the advantages of using Walsh Codes and when to use them , similarly for Pn sequences ... there are also Gold codes , why arent they use...
PN sequences are also used in cdma for spreading , so if PN sequences also provide orthogonality and PN sequences also , then when to use Walsh codes and when to use PN sequences , i know read some where that Walsh codes are used in Synchronous CDMA and in Asynchronous CDMA PN sequences are used...
we use walsh codes in cdma (synchronous) , because they are set be orthogonal , when we say orthogonal signals , what do we mean physically ? mathemetical iterpretation is clear that two walsh codes are orthogonal because they have equal no. of 1's and 0's , and scaled dot product of code is 1...
UART
I HAVE TO USE UART RECEVER IN FPGA , TO GET SERIAL DATA FROM A COMPUTER IN FPGA , I HAVE SOME QUESTIONS REGARDING THAT
1. THE BAUD RATE U SET N UART , IS THAT BAUD RATE(SYMBOL RATE) EQUAL TO BIT RATE ? BECAUSE DATA IS COMING SERIALLY TO FPGA i.e ONE BIT AT A TIME
2. SECONDLY WHATS THE...
AWGN TESTING
HELLO .. I want to test my transmitter for AWGN .. i have coded my transmitter and receiver using VERILOG hdl .... kindly if anybody has verilog code for AWGN .. where i can change SNR values .. and calculate BER for each SNR.....any suggestions for simulating AWGN and calculate...
HI ... I WANT to send sampled & quantized voice in fpga .. now the problem is that i dont have a ADC or DAC ....SO i can use matlab ... now how can i translate voice , may be from VOICE RECODER BLOCK IN SIMULINK ... OR ALREADY PRESET .wav file , into 1'S & 0's .. any body having any matlab...
HELLO i am using a jtag-parrallel Cable III......TO CONFIGURE a SPARTAN 3A 1800 FPGA STARTER PLATFORM.... I GET THE ERROR : '1' Programming terminated.DONE didnot go high.
complete text apperaing in PROJECT NAVIGATOR space is :
"
// *** BATCH CMD : loadProjectFile -file...
HI ! i have a usb-JTAG CABLE FOR PROGRAMMING A FPGA , there is no mention of any vendor or company on the cable .... when i used it to program a XILINX SPARTAN 3 E FPGA ON A DIGILENT BOARD THROUGH "ADEPT(SOFTWARE I DOWNLOADED FROM DIGILENT.COM)" , the bit file was successfully downloaded to...
HI . kindly some one tell me : how to integrate VERILOG written code and XILINX SYSTEM GENERATOR design together for FPGA implemenation.
means that i have some part of my complete system, designed in XILINX SYSTEM GENERATOR and some part i have written in VERILOG .. so Can i make a SYSTEM...
hi kindly someone tell that how to make a block of walsh code in SYTEM GENERATOR ..in SIMULINK there is ready made block of walsh code but in system generator there isint ..... i need to implem,ent cdma on fpga so i need walsh code block in system generator .... kindly tell ..thanxx
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