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Its all working now :-) it was as suggested timing issues, ive generated a the clock with a pll and everything is behaving as should.
Forgive the typos the actual code was enormous mess from days of frustration hence port labelled in various different ways. The shifting etc was removed to...
Hi guys ive been playin around with altera fpga's for a while and managed a few basic projects but im struggling with this one and none of the books and tutorials ive got seem to help (i think it might be a timing issues)
The code is for a very basic spi master that esseential just transmits a...
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