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Recent content by haribabu

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    CMOS relaxation oscillator Design ...

    Hi LvW, Thanks for your patient reply. I could get the operation of the relaxation oscillator. But i couldn't get how Razavi says the circuits oscillates (assuming linear model) meeting the Barkhaseun criteria with the transfer function given in the paper.It has one zero at origin and two left...
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    CMOS relaxation oscillator Design ...

    You get a Warning! Do not upload any IEEE copyrighted papers. You will be banned Hi LvW, i) If not through Barkhasuen criteria, Can u please provide me the explanation for the operation of the above circuit ? ii)In the following paper section-VII explains it operation through Barkhasuen...
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    CMOS relaxation oscillator Design ...

    Hi Saro, It has been long time since i posted this message. I have quick doubt here. Since it is a relaxation oscillator without the crystal, i want the check the Barkhausen criteria for this circuit . Redrawing the above circuit as i) To satisfy the phase criteria of 360° each stage has to...
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    Phase Noise analysis of Crystal oscillator in Hspice

    Hi all, I want to do the phase noise analysis of crystal oscillator in Hspice/HspiceRF. Can any one post me the test bench or tell me the procedure to do it . Thanks Hari.
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    32KHz oscillator architecture with < 1uA current.

    Hi All, Can anyone suggest me on choosing to architecture for 32KHz oscillator with targeted current consumption < 1uA. As a first cut I have taken the architecture from Vittoz paper on 'High Performance Crystal oscillator circuits'. Are there any other architectures ? . Thanks Hari.
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    Hspice options for Crystal Oscillator !!!

    Hi ankit, Thanks a lot ....Its working ...
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    Hspice options for Crystal Oscillator !!!

    Hi, Can anyone suggest me on the hspice options required for running closed loop crystal oscillator simulations ? ... The reason for asking the above question is that even though the negative resistance of the circuit is about 1.5 times the crystal resistance, I do not see any oscillations at...
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    CMOS relaxation oscillator Design ...

    Hi Saro, Thanks a lot ... Ur expertise in oscillator design made my task easy . Are there any mathematical relations that help me in choosing the value like Cs ( capacitor between two source) and the filter R & C values . What happens if we directly connect gate of the bottom transistors to the...
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    CMOS relaxation oscillator Design ...

    Hi Saro , I am looking for a crystal oscillator behaviour and not the relaxation behaviour. Thanks for your very useful reply ... The following post is very helpful ... I found the mistake in my ckt, which is because of using ideal current sources (derived from a current mirror ckt .) instead...
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    CMOS relaxation oscillator Design ...

    Hi guyz Thanks for taking time in giving reply.I am attaching my reference paper from which i got the above circuit . @dick_freebird I am looking for low power crystal oscillator circuit .I already have my inverter based crystal oscillator ckt . designed but the power consumption is huge (10mA...
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    CMOS relaxation oscillator Design ...

    Hi ... I am designing a cmos relaxation oscillator connected to a crystal . My circuit look like this .. I connect the crystal working with resonance freq at 50MHz between the two outputs. The issue is, there are no oscillations produced at all .The circuit is getting latched .I measured the...
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    LVDS tx at 1.8v supply - tfall and trise problems

    Re: LVDS tx at 1.8v supply I checked it ..They are almost equal .I c only 100uA difference between them ..
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    LVDS tx at 1.8v supply - tfall and trise problems

    Re: LVDS tx at 1.8v supply Common Mode Offset voltage is the deviation in the Common mode voltage from its typical value (i.e 1.25 v )
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    LVDS tx at 1.8v supply - tfall and trise problems

    Re: LVDS tx at 1.8v supply hi , The pulse widths for the clock are equal !!!!
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    LVDS tx at 1.8v supply - tfall and trise problems

    LVDS tx at 1.8v supply Hi , I am designing a LVDS tx at 1.8v supply voltage .Since at lower voltages the headroom available for the upper current source is less , i used normal current mirror at the top and cascode current mirror at the bottom . The problem now is i am cing my rise time to be...

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