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Recent content by hari151087

  1. hari151087

    AOCV - Advanced On Chip Variation

    Thanks for sharing ..!!
  2. hari151087

    Chance to enter into vlsi field

    This is a Great oppurtunity to You Guys As I was one who wrote that exam and now in AMD. I Suggest all the people who are Interested in VLSI can try this exam ..!!
  3. hari151087

    Chance to enter into vlsi field

    Syllabus : 1. Digital Design & Micro Processors 2. C Programming 3. Aptitude
  4. hari151087

    Chance to enter into vlsi field

    ‘VEDA IIT Recruitment Test’ is scheduled on 2nd April 2011. Apply online at Veda - VLSI Engineering&Design Automation before 30th March 2011. VEDA IIT Recruitment Test Details: Exam Date : 2nd April 2011 Exam Time : 10:00 A.M Exam...
  5. hari151087

    make our group active

    i think to post any Job related stuff , latest happenings in market , Guidance to Our fellowmen etc will make this group active
  6. hari151087

    what can i do to make this blog better

    Yaeh this group is inactive we have to make it active lets shre our difficulties faced in entering into this field and help our Juniors ...!!!
  7. hari151087

    cadence soc encounter fetxtcmdref needed

    Re: cadence soc encounter fetxtcmdref needed Thank u very much Hairo...
  8. hari151087

    new to asic and need help

    Drc and lvs should met before tape out as our friend said
  9. hari151087

    new to asic and need help

    YuLongHuang and we need to use prime time to dump sdc files which are inputs to Encounter or Synopsyis Tool ---------- Post added 09-02-11 at 00:01 ---------- Previous post was 08-02-11 at 23:54 ---------- step 1: netlist which u hav step 2: convert that Netlist to synthesised Netlist using...
  10. hari151087

    query regarding symmetric buffers

    Thanks phoenixpavan
  11. hari151087

    query regarding symmetric buffers

    why is it necessary to have only symmetric (equal rise and fall time) buffers in the clock path ?
  12. hari151087

    [SOLVED] query regarding transition voilation ??

    Thank u lostinxlation
  13. hari151087

    [SOLVED] query regarding transition voilation ??

    why there is a need to clear transition violation even after Timing is cleared ??? and Do we need to consider tran voilation even in hold mode??
  14. hari151087

    clock tree synthesis questions

    Thank you guys, it was helpful
  15. hari151087

    Best VLSI Institutes in INDIA

    veda iit is very nice platform for any aspirer who do wants an entry level in vlsi companies like AMD and soctronics. they are getting tieups even with us US companies like silicon image which is good indeed. actually i am recently done with pnr training in VEDA. and got placed in AMD,Hyd...
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