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Hi friends,
I have to communicate with a radio which have SPI interface but my PC doesn't have SPI interface therefore i have decided to accomplish my task by using arduino as a interface between PC and radio. Now i want to send my HEX data serially to arduino, store it then send it to my radio...
Dear erikl
i have already lower the values of output capacitors and got unity gain frequency around ~1.6 GHz with 58 Degree of phase in pre layout, and after re modifying the output path in layout the post layout results are changed to 950 MHz with 65 Degree of phase.
Can you suggest some more...
Hi,
I have Layout the design of Gain Boosting Op_Amp but i am experiencing a major issue in post layout that its Unity Gain frequency is going below half of the total,
My gain boosting op_amp is designed for 1.3 GHZ with 77 Degree phase, but in post layout after every effort i managed to get it...
I am recently shifted to 40n technology from 65n technology ,
In 65n Technology my LVS always show Diodes errors which i resolve by placing a pair of reverse bias diode in schematic.
But now in 40n technology There is no diode errors present in LVS even if my designer place diodes in schematic...
Thank you so much,, i have pretty much figured out the problem by changing the capacitive sensitive nodes to higher metals as higher metals have low cap/sq value. and also i have routed those nodes in a very calculated manner which helped me to get the phase difference from 22 to 10 degrees. :)
Yes before simulation all results are fine but after post layout simulation the designer told me that my layout is not satisfying the phase and around 20 degree phase is decreasing.
Hi,
i am designing a very big layout and now i am wanted to make individual cells on the of the different portions that i have created as they will not annoy me anymore , so that i just pick and drop them where ever i want them to place ,, please let me know a procedure so that i make cells of...
hi,
i am new analog layout engineer, the problem i am facing in my layout is with the phase margins and gain margins, the designer is not satisfied the phase and gain margins of my circuit, please let me know what precautions should i follow to minimize these errors.
Thank ou so much for replying well I am using 65n technology and and have set my Grid to 0.005. i only able to draw path with the width of 0.24u, i have also have tried many other width sizes also but DRC is not clearing them.
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