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Hello,
As a part of my master thesis i need to formally verify with completeness that the AHB
system I am using works as intended. I am using a vhdl ahb system generator found online, but
I wrote simple masters and slaves myself, so I need to make sure I haven't misunderstood the spec.
It...
I read somewhere someone advocating the use of multilayer as most slaves aren't split capable anyway, therefore saving area on arbitration
logic and less complex masters. But if I understand correctly, each master has its own interconnect layer so the area argument doesn't seem right.
What...
I tried posting this thread earlier but it just vanished, so hope it doesnt appear twice.
I am doing a masterthesis where the AHB protocol is a central subject, and I am confused about
where we use multilayer AHB-Lite instead of AHB.
I should not describe all the details as it is not...
Hello,
I am trying to implement a 2.order IIR filter using SystemVerilog, and I am having some trouble.
a0*y[n] = -a1*y[n-1] - a2*y[n-2] + b0*x[n] + b1*x[n-1] + b2*x[n-2]
The simulation results i get using a square wave input and low- or highpass coefficients is garbage, but when running...
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