Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
PLL is used to feed the grid angle to the vector controller which is the main controller to drive the converter in unity power factor. So use vector control method. The idea is to set the q component of the grid current to zero hence align the d component with voltage vector. The park...
for the clamped mode, yes Q2&Q3 will be on. for the timing issue, with high power application and +400Vdc, short circuit definitely will take place for few microseconds but when supplying inductive load, that time will prolong and IGBT will be stressed till get damaged.
I have no other circuit...
* Circuit used before for three phase 2 level IGBT inverter.
* no timing can be implemented in software as it is just less than 10 micro-seconds
* delay is not external unknown. delay is internal function in IRxx to prevent short circuiting the "H" and "L" IGBTs at the same inverter leg
true except for the delay time. using opto-coupler with TIP122 transistor has also led to IGBT failure. so, the most important feature of IR21xx is its internal delay between HO and LO.
still on my opinion that IR2110 is the only secured option to drive the NPC scheme.
The only advantage of using IR is the internal delay which prevent Q3 from being on while Q1 is turning off. In other words Q3 will conducts only when Q1 is totally off.
this is the simulation when I removed the first GND point (upper). Bootstrapping is clear. as I expected it is a capability of simulator.
Green: HO
Yellow: Vs
I must use IR for switching delay facility as you are fully aware. I am not trusting LTSpice for that schematic because I am not sure that it has a grounding isolation facility in simulator. two weeks ago, I contacted IR for advise and they are so reluctance to give help as the NPC application...
just look to the IR2110, can it work like that. I think the problem of LTSpice simulator that we can not isolate the grounds. for real simulation I should have the facility to isolate grounds but I can not find a way. is there any tricky way to do that.
specifically those two grounds are isolated from IC ground. the simulation results seems ok by LTSpice. for each IC I have three isolated +15 sources. please check the design as per attached below,
I am online with simulator so any test required?
Good idea according to the design I will use three 15v supplies with separate grounds for each IR. so IR1 will supply Q1 and Q3, IR2 will supply Q2 and Q4.
Thanks for your reply. my intension is not to discuss the theory of operation, I am focusing in implementing the IR2110 to build he IGBT drive. if you can find any post dealing with that issue you would offer me a great help
best regards
Hany
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
