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Hi batman!
M1-M3 is indeed a Diff Pair, and M4-M13 is a folded cascode. The structure M10,M12 is a self-biased cascode (gates connected together). That structure, and also M11,M13 and M15,M16 are the outputs of a current mirror whose input looks the same. That input generates Vbias. This makes...
I guess you'll have to read something about Sigma-Delta. I suggest you read this:
https://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html
If your confusion persists afterwards, you can always ask more questions.
Slainte!
H
You are raising a very difficult point here. 1/f noise is only quasistationary if the time scale you are looking at is relatively short compared to the time that has passed since the flickering system has been switched on. Right after switch-on, it is not even quasi-stationary. This also has...
Hi everybody! Virtually everything said here is true, but you don't answer the original question:
Flicker noise is indeed not stationary. As you can see in Fig. 4 of the Flicker Noise Chapter of the CRC Book Circuits at the Nanoscale: Communications, Imaging, and Sensing...
Very simple: The simulator is the problem :lol: For high Q factors, it will not work properly with the standard integration method due to numerical problems.
Use the integration method traponly, and it should work.
Please note that then some of the curves you will see may look like a zig-zag...
Hi Sam,
If you go so far below VSS, then the transistor whose gate is connected to that line needs to be a high-voltage transistor. You'd protect that one from an ESD event using SCRs (silicon-controlled rectifiers).
Then you would have that diffusion area you need against antenna charge...
Hi Dick! All this is true, but it will still be forward biased when that N+ contact is 1.8V below the substrate, which is what Sam is doing.
What I'm trying to find out with my SCR question is whether Sam already has a leakage path that would prevent a voltage build-up due to antenna effects...
Don't worry, Slainte! simply means "health!"
I assume VDD=1.8V, VSS=0V. Therefore your line can go to -1.8V, approximately three diode voltages below the substrate. Protecting a line whose voltage can go 1.8V below the substrate voltage against antenna effects is no trivial matter at all. It...
:)))
Slainte is a Scottish greeting :) My name is Hanspi, which is short for Hanspeter.
Regarding diodes: all depends on how much "AC" your signals are. What is VDD, and what is the min and max voltage on the line you want to protect?
Slainte!
Hanspi
It does not matter. In fabrication, during metal deposition, a charge may build up on the metal being deposited: this is the Antenna effect. As long as a diffusion area is conncted to that metal line during depositon, the charge will leak out quickly enough such that the voltage does not buold...
Since the µ depend on doping, and customers of foundries normally want to use similar designs when going to a smaller technology node, I can scarcely imagine what could bring a foundry to doing this 4.7 ratio ... they'd have to do it on purpose, but for what purpose?
Scottish ... I studied...
Everything you need is described above in this thread: read it attentively :)
I have a comment, though, on the page you show as an image from David Binkely's book. The values for carrier mobility are strange. Both UMC 0.18u and TSMC 0.18u have a carrier mobilty ratio of approx 2.6, not 4.7 as...
Hi godfrey,
yes, erikl's circuit suffers from the same problem.
If you increase the resistors to 100k each, even a 100fF capacitor at the diff-pair input will increase the time constant to 5 ns, resulting in a not so steep slope of the diff-pair control signal. If that slope is not so steep...
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