Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello,
I have an VHDL-Project on Quartus Prime Standard 22.1 which I want to test using Questa FPGA Starter 2021.
When running the testbench i have to Problem tha some signals are not shown to me.
Using the same testbench and entity on an windows PC lets me see the signals.
So i think this issue...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
