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local skew
locak skew: skew between the launch reg's clock and the capture reg's clock
global skew: the max skew in the clock tree
If any error,please correct me
As an soc design engneer, we often focus on rtl design, verifcation, dft and sta...
But do you want to be a soc project manager?
And how to do that?
We should know risk control, resource management ,time control and ....
Can you give your tips ?
need for process
Dose flip chip need more process step than wire bond chip in foundry?
When are the UBM and BUMP added to the filp chip die? Before scribe wafer and after scribe wafer?
And if before scribe wafer , can filp chip die and wire bond die be produced in one wafer when MPW?
I am...
Which aspects should I consider for?
IO number? CLK frequency? ATE memory depth? Analog and RF module?
And the IO number of the IC must more than the ATE IO numer?
die size and pad numer
Thx.
I have used staggered pads.
Flip chip will need more money. And I am not familiar with the FC‘s backend flow。
Can you tell me the difference between the nomal wire bonding PR flow and the FC's PR flow?
Added after 1 minutes:
Can anyone explain the "multi tier...
die size staggered pad
Hi,all
In my project, die size is not big engouth to place all pads which use wire bongding.
How can I slove this problem?I dont want to add the die size.
Thx.
I am designing the SD card controller IC.
which type pad should I select to connect with SD card?
SD card's IO is push pull circuit.
How can I select controller IC pad's drive capacity? About how many ma pad should I select?
Thx
ATPG simulaiton failure is because I have not back annoted sdf file.
With sdf back annoted, atpg simulation will pass except only two cell's error in one chain in a little few pattern . Why this ? I want to mask these two cells when run ATE test. My test coverage is 98%.
Another question, How...
In my soc, there are some clock sync DFF. For example, in usb module, there are some DFFs use clk_48 as clock and clk_12 as data, that means in normal function mode DFFs will use clock of clk_12 as data. But in scan mode, clk_12 and clk_48 will be one clock, that is test_clk, then in scan...
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