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It has to be somewhere inside your .cdsenv or .cdsinit (not so likely) or you are loading another setup file maybe local .cdsenv after the default ~/.cdsenv
If you are still having problems try to change the simulator to spectre and than save the .cdsenv by options -> save defaults...Good lack
I was talking about IC not board design
Anyway, I got to the conclusion that anyone who experience with multigigahertz analog designs will will be able to handle RF layout easiely. or not...
"Spectre provides the SPICE Reader to let you simulate existing SPICE netlists with Spectre"
I think that this feature exists only in version 5.0 and above
Read the documentation
VCXO
Hi All,
Did any of you ever design vcxo? Can you offer a starting point - which architecture etc.
I'm talking about 80MHz vcxo with 1pS RJ.
Thanks for the help
rf layout
Hi All,
Can anyone tell me what is the difference between analog and RF layout? Can analog layout designer do RF layout in bicmos process?
Thanks
hot n-well
Usually, hot n-well in nwell that is not connected to VDD.
You should check that the Nwells are connected correctly to VDD. If you want to connect the nwell to different potential,I think that you can ignore the warning.
Re: Gate Oxide Capacitor
The problem is TDDB which cause reliability issues. Let's say avarage life time of mos is x years under some conditions. Statistically, about 1/2 of the time the voltage across the gate oxide will be VDD. The voltage across decap will alwayes be VDD so it's lifetime...
Re: Gate Oxide Capacitor
One thing to notice.
In 0.18u and below,using thin oxide devices as capacitors (i.e connect the gate directly to VDD) is usually not recommended as it may cause reliability problems.
Just keep in mind
Re: VCO architecture
Ring oscillators CAN work even at 5GHz in 0.13u process.
The problem is the generated noise of the VCO, so if one can afford BW large enough and not concerned about jitter transfer, I would definitely choose the ring oscillator.
I am using Virtuoso XL for few years and quite happy with it. The new version of cadence ic tools (5.1.4.1 I think) has some improvements for analog layout design, but I have'nt tried it yet. Can someone can share his/hers experience?
Re: Common centroid
I agree with Colbhaidh.However, the small device 2.4/0.8um may suffer from Vt mismatch due to it's small area (roughly 10mV, depending on your process). If this is current mirror, you might want to use larger devices.
Common centroid
Hi All,
I know that common centroid method has been used for quite long time in order to improve matching.
I never used common centroid or interdigitate methods for matching. I use large area devices and place matching devices close to each other, and I never had mismatch...
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