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Ok, I have made certain changes and now I am getting a parameter mismatch and net mismatch. In parameter mismatch, it says size of 4 transistors are different in schematic and layout, but I generated these transistor layouts from schematic itself. And I am also getting 6 label shots
Here are...
I am doing a LVS match of a 6T SRAM using 180nm technology. First I made a schematic of 6T SRAM and then generated the layout from schematic using Layout XL , and made some additional routings. i successfully ran the DRC. But while doing the LVS match I am getting the errors like one...
I have typed a verilog code for a simple half adder block using cadence.
I have compiled the program and it does not show any errors.
when i used the tcl script.
"irun -clean *.v -input probe.tcl -access +rwc -timescale 1ns/1ns &"
the files get compiled and simulate too.
when when i run the...
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