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Recent content by guybrush

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    MAXIMUM LOAD FOR FPGA IO

    maximum capacitor load fpga Dear all, I'm designing a memory interface where a lot of memory chip are driven by an FPGA so that the capacitive load on the PCB track becomes high. The effect will be 1) Increase of delay 2) Slow edge on the signal Can this second effect cause problems? Each input...
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    please help! vhdl square root

    Why not using Cordic?
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    DOLBY DIGITAL DECODER AND AUDIO AMPLIFIER

    But the Dolby digital 5.1 is compatible with the AC-3 standard ?
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    DOLBY DIGITAL DECODER AND AUDIO AMPLIFIER

    Hi to everyone. I'm thinking to build my own multi channel amplifier for music and also for home cinema. For the audio section, there are a lot of material on the internet. For the digital section, is more difficult to find material. There is some chip from zoran.com but i don't know if the algo...
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    Looking for resources about graphic file formats

    Graphic file formats Hi all. I'm searching for a book or a tutorial dealing with the graphic files formats. I have found something on the net http://www.dcs.ed.ac.uk/home/mxr/gfx/index-hi.html http://www.faqs.org/faqs/graphics/fileformats-faq/part3/ but i hope there is some more. Could you...
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    What is the best method for PCB layer stacking?

    fast signals inner layer ground plane I all. I'm designing a digital board with 2 power planes, a ground plane, 9 signal planes. Which is the best approch for the stacking of these planes? Is there any book adressin the problem of layer stacking in order to minimize EMC/EMI and to have the...
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    Line impedance of a PCI backplane design

    Hi all. I'm designing a PCI backplane with 4 slot. Each slot has a PCI interface with 3.3V signaling and the bus speed will be 33MHz. Two interfaces will be designed using an Actel A54SX32S FPGA and a VHDL core. I read the PCI spec and now i have to choose the impedence of the line into the...
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    PCI bus interface question about signaling voltage

    qs3861 pci Hi all! I'm starting a new design which deal with a cPCI inteface. I know that the computer board as a 5V signaling. This mean that all the board into the bus must have a 5V signaling or at least be 5V tolerant? An FPGA that can't tolerate the 5V will blow up? Thank you
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    "clock skew"-"clock delay"......PLL-DLL

    Re: "clock skew"-"clock delay"......PLL- Skew is the maximum of the clock delay difference between any two piont into the device where the clock is routed (FF clk input)
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    Opinions on QuickLogic FPGA user-friendliness

    otp fpga Yes, also Actel are OTP
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    How to generate 2 clock outputs in ISE 6.3?

    Re: how to generate clock Use DCM
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    Delaying signal in Actel FPGA

    DELAY IN FPGA (SDF file) Hi all. I have to implement a 50 ns (nominal) pulse, 200 KHz using an FPGA that has a 2 MHz clock. I'm using an ACTEL fpga and the envirommental constraint are -25/+90°C. Since it is imposible to produce a 50 ns pulse with a synchronous logic clocked @ 2MHz, I decide to...
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    May FIFO be read and writen simultaneously ?

    You can read the fifo while writing if the number of word in the fifo is greater than one. When the fifo has one only word, there is the risk of collision of the read and write address.
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    Whats the best solution for dividing a serial receiver?

    Re: SERIAL RECEIVER But as far as the power consumption i think this is not the best solution. I think that the third solution could be the best. I don't find any problem with that implementation. Maybe in my next design i'll exploit this solution.
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    Whats the best solution for dividing a serial receiver?

    SERIAL RECEIVER I'm designing an ACTEL A54SX FPGA for control and monitoring of a power board, implementing two serial interfaces very slow (19200 bit/s, with parity) and some digital I/O. On the board i have a 8MHz clock, so I have to divide it down to 8x19200, that will be the higest...
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