Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by grvkpr18

  1. G

    How to borrow time in STA?

    I guess this link will help you understand better. https://vlsiuniverse.blogspot.in/2016/08/time-borrowing-in-latches.html
  2. G

    [SOLVED] Can metastability occur on a latch ?

    Latch will go metastable at the closing edge, not the opening edge. It can borrow time only for the opening edge. When data toggles near the closing edge, it can go metastable.
  3. G

    Yet another lockup latch question

    Hi Both + => - and - => + dont need a lockup latch as the hold requirement for them is half cycle. This is a good article I found on the web related to this. https://vlsiuniverse.blogspot.in/2013/06/lockup-latches-soul-mate-of-scan-based.html
  4. G

    Bipolar process(MicroElectronics)

    I think this is because BJT's operate at higher voltage than CMOS. The current levels are high. So, they can drive higher loads as compared to CMOS.
  5. G

    how to apply multicycle path on data to data check

    Hi If both data and address bits are constrained with respect to the clock, should there be any need for data check between them as they will have a relation between them too.
  6. G

    effect of duty cycle on clock power loss

    This depends on whether your design is level triggered or edge triggered
  7. G

    cadence technology file

    you have to buy it.
  8. G

    How to Create energy ?

    If you can create mass, you can create energy according to einstein's relation.
  9. G

    a user friendly xilinx tool through java codings

    WE have to simulate or to synthesize a program in xilinx through java codings....plz give some solution as soon as possible...
  10. G

    Binary representtion of prime numbers

    i dont think there is any method available for your help.
  11. G

    Problem in importing verilog netlist through verilogIn in virtuoso

    Sir,, Symbol are there. But it doesn't seem to find any matching description for those symbols. Like there should be any schematic or verilog ams description i thinl
  12. G

    Verilog HDL problems pls help

    You must have declared KEY as an input. Inputs cannot be manipulated in the program. I think you should rewrite KEY as inout.
  13. G

    the algorithm which find a word

    can you elaborate please?
  14. G

    Problem in importing verilog netlist through verilogIn in virtuoso

    I am trying to import verilog netlist in virtuoso composer schematic view so that we can interface analog part with the digital one. But I am facing some problems. 1. The reference library I am using consists of faraday standard cells of UMC 180 nm technology. The reference library has only...
  15. G

    How to create a current source

    Hi all. I need to create a 5 amp current source . load varies from 50 to 100 milli ohm? Can any one help me ? Any way without using current transformer ? thanks for help You can use power transistors in current mirror configuration.......i think that may help you
See more

Part and Inventory Search

Back
Top