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Many thanks for all your help ads-ee! I have decided to go with the trickle-down parameters like you suggested. I already have a basic version implemented.
Sorry, no, I miswrote.
There will never be two modules that need to write the same bit at the same time (hence the merged A/B write), however one module may write it and another module may read it. This is in addition to read access via the "external" interface to my core.
Thanks for the feedback! I need to change it so that ports 1 and 2 can write at the same time if their addresses are different.
If port 0 writes to the same address as 1 or 2 then ports 1 or 2 get priority as I mentioned in a previous post about simplifications.
Here is my issue and perhaps...
OK, thanks. Here is what I have come up with. This is inside a clocked block:
// writing - port 0
if (Write_0) begin
if (Address_0 < `REG_NUMBEROFREGISTERS) begin
Registers[Address_0 * 8 +: 8] <= DataIn_0 & WriteMasks[Address_0 * 8 +: 8];
end
end
// if writing on ports 1 and 2 at the...
vGoodtimes has exactly what I was thinking. I will post my code when I have tested it this evening or tomorrow. Meanwhile I am working on the masked write part for ports A and B. Essentially what I want to do is a read-modify-write in a single clock cycle. Here is my code:
Registers[Address_1 *...
Thinking about this a bit more I am wondering if I can make some simplifications.
1. A and B modules will never need to write to the same bit.
2. Any bits that A and External can write to or B and External can write to should give External the lowest priority
I was therefore thinking that if...
Sorry, I shouldn't have used the term 'RAM'. This is implemented using flip-flops, as an array of groups of eight.
reg [(8 * `NUMBEROFENTRIES) - 1:0] Registers;
It sounds like I am not trying to do something completely wacky, which is good. :)
I have a module defining some memory, e.g. an array of 8-bit wide registers. These have read/write access from outside my core ("external") using a typical 8-bit-wide bus.
From inside my core ("internal") I have two modules A and B that also need read/write access, however for some registers...
Hello, using Verilog and I am creating a 'memory', e.g.:
reg [7:0] registers [0:4];
This memory is read/write accessible via a bus, and some of the bits will be read only and some will be write only.
I am trying to construct a "core-wide" set of definitions to use throughout my core so I can...
Hi, I am learning Verilog and struggling with an aspect. I have an 8MHz clock and I have an external signal called Rxd. I need to detect a falling edge on this signal and reset a counter. It could be anywhere from ns to hours before the falling edge appears.
I have:
reg Rxd_Buf;
always @...
The best I can do is remove the copper pours. Here it is.
Thanks for the suggestion about the grounds on the decoupling caps. I've made some tweaks to hopefully improve that.
Here is how it looks now.
I decided to stay with the thermal spokes for the pads, but removed them for the stitching vias.
I don't see any easy way of increasing the thickness of tracks entering/leaving pads in my software. I would have to create small track segments and individually...
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