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Recent content by gpwu

  1. G

    PhD in Analog IC Design - Help

    In my opinion, the adviser is more important than school. Best find a well known analog professor to be your adviser.
  2. G

    how to simulate capacitor mismatch of a pipeline SH circuit?

    #1 Calculate the caps mismatch from foundry's matching table. #2 Put this value, for example, a small cap represent the mismatch into your simulation
  3. G

    compensation in folded cascode OPAMP

    1. increase output cap 2. lower low impedence nodes R & C
  4. G

    Help me design an op-amp for an integrator circuit in 12-bit ADC

    accuracy integrator circuit 1. increase tail I to increase BW 2. reduce parasitic caps to increase feedback factor
  5. G

    suggest me a good book

    Razavi's analog book
  6. G

    Max possible precision in analog circuit

    But by using oversampling technique, you can push noise to higher freq and then filter it. So, it's possibe to achieve resolution > 17 bits at low freq. Lower signal swing, lower resoution.
  7. G

    What's the mininum PLL phase margin for the loop to work properly?

    PLL phase margin thank you guys for your help..this is a good forum. Hope I'll post some better questions next time.
  8. G

    Dose Analog IC Design & Layout have a good future?

    rikie_rizza, I like your suggestion, though it's too late for me!
  9. G

    how to implement this function?

    1. put Isig=0, measure V(t2-t1)=dv1 2. add normal Isig, measure V(t2-t1)=dv2 Then the dv2-dv1 should be Isig's contribution
  10. G

    How to calculate the THD of sample and hold circuits in Cadence?

    Re: THD of S/H circuit Feed the output to the FFT program.
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    Dose Analog IC Design & Layout have a good future?

    Auto analog layout will replace manual layout in the future in my opinion.
  12. G

    comparators with 1.8V power supply

    You can add another pdiff pair inputs, so it can work over large input range.
  13. G

    Differences between types of PLLs

    Re: Regarding PLLs - Deskew PLLs : outputs and input have same phase, limited freq selection - Clock generator PLLs : generate a wide range of output freq - Spread Spectrum PLLs : similiar to Clock generator PLLs with EMI reduction of peak energy - Low Bandwidth PLLs : PLL has a low BW, good...
  14. G

    Relationship between Vdssat and Vov

    vov transistor For long channel, Vov = Vdsat, IV curve looks like sqare law. If same Vov as above for short channel device, Vdsat < Vov because higher field & IV curve looks like linear.
  15. G

    Basic question in analog design

    Longer L will have less channel length modulaiton, therefore, higher gain which is important for analog circuit. Digital circuit need less delay, so minimum L&W is important for speed and lower power.
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