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Recent content by Goldeneagle

  1. G

    Need interview questions on Advanced Floorplanning techniques ?

    Hi Pavan, 1. Macros are aligned such that the pins, pin orientation, channel between memories, any extra spacing to be left around, their power source are taken care. Overall the macro placements have to give close to rectangular space for the standard cells. Secondary issues have to be taken...
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    .MEASURE usage in HSPICE for find the max value

    Yes.. as of now i hav taken that approach... but i hav 2 sets of 12 variables each.. !! so its quite a clumsy deal !!
  3. G

    How to determine the exact dimensions and spacing for probe-pad design?

    Re: Probe-pad design Are you talking about only the Probe pad design or the IO buffer associated with it ?
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    How to measure VIH at normal range 2.5V CMOS(JESD80,JESD8-5)

    Re: How to measure VIH at normal range 2.5V CMOS(JESD80,JESD If you are running your spice simulation.. then you can sweep your input DC voltage from 0 to VDD and then check at what input voltage the output changes to High.. VIH is basically the min input voltage at your input pin that can...
  5. G

    what are remedies for IR drop

    For static IR .. you can even widen the metal if there is room for doing so..
  6. G

    Increasing Frq of operation

    U r question has lots of possibilities.. So r u lookin at porting them or designing in same technology node ?? If so watz the max freq of operation beyond 100 MHz ??
  7. G

    combinational circuit design:RTL to GDSII

    I guess u can put an flop at the inputs and the outputs.. and constrain them using virtual clocks..
  8. G

    can any one explain me what is a prBoundary

    Well analog cells would be definitely used as macros at the top level.. prBoundary defines the boundary for the cell/macro.
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    What are tools available in market to measure IR drop?

    Apache tools are equally good.. Check Redhawk..
  10. G

    switching speed... and the switch driver

    Do a simple tran.. measure the input cap of both the switches or just the second switch.. that can be considered as the load for the prev stage..and then resize your previous stage to meet ur timing.
  11. G

    Cadence DRC error messages

    As the other 2 fellas suggested.. these errors are bcoz of the tap not being placed. Did u get it resolved ?? -Viv
  12. G

    Positive skew and negative skew

    Hope this helps.. https://en.wikipedia.org/wiki/Clock_skew
  13. G

    .MEASURE usage in HSPICE for find the max value

    Hi, How do i measure the max value among a set of values say from n1 to n10... where n1 to n10 are the timing delays measured using a different measure statements.. like.. .mea tr n1 trig .... targ... .mea tr n2 trig .... targ... .mea tr n3 trig .... targ... .mea tr n4 trig .... targ... .mea...
  14. G

    circuit of fsk modulation & demodulation with xr2206, xr

    Re: plz kindly help me out These links should give you a clear picture... http://www.datasheetcatalog.org/datasheets/134/500366_DS.pdf **broken link removed** Hope this helps...
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    Lab Guidance for PRIMETIME

    If ppl are using the synopsys primetime tool already.. then i guess you have a tutorial in the path where the tool is installed/accessed from.... <Installed_path>/synopsys/pt/<version_no.>/doc/pt/tutorial/.. Just search in the dir structure and u shd b able to find the tutorial and the need...
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