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Hi all,
I need to Initialize all the data RAM to $55 (use a loop for this) in verilog.
The data ram memory size is 256.
We need to Initialize memory using software and not hardware.
Can anyone pls help me resolve this issue..
Thanks in advance..
Hi all,
Thanks for ur answer. its works.
i got some warning like Tri state node(s) do not directly drive top-level pins
Is this warning matters or not... coz when trying to generate functional simulation netlist, am not getting the wave from file.
Can anyone pls help me to resolve this...
[/code]
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity datapath is
port( reset, clk, start: in std_logic;
mainout: out std_logic_vector( 7 downto 0 )
);
end datapath;
architecture struct of datapath is
component controller is
port( clock,GO,rst: in...
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