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Recent content by Godup

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    Comparator challenge (FPGA)

    Hello, still designing a comparator (VHDL) and i want to assign an input pin with a fixed gain/ref (e.g 00001100). How am i supposed to assigned this width to the FPGA??? Is it compulsory i attach a daughter board (DDR memory) and assign this data to it or i can simply pick any of the...
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    Comparator challenge (FPGA)

    In time past i had encounter with the "differential pin pair"... "DQ" were mapped with "DQ" and "DQ" were mapped with "DQS". Where mapping such as (DQ & DQS) both came up HIGH when either of them are assigned as output pin and vise versa. Though not so with same mapping (DQ & DQ). Which one of...
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    Comparator challenge (FPGA)

    . Saw something like that on the pin planner. an icon (differential pin pair), is that what u meant by differential input??? some where labelled "DQ" and some labelled "DQS". Does assigning analog voltage with different voltage level (e.g 1.0v and 3.0v) cause the comparator sense voltage...
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    Comparator challenge (FPGA)

    Hello frndz, Again, i want to design a comparator that can compare two analog voltage (e.g 3.0v and 1.5v) for a STRATIX III FPGA. Meaning my design is supposed to be digital using VHDL. The comparator is should be sensitive to the input analog voltage such that voltage 3.0 to 2.5...
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    Ring oscillator design

    Not too sure about syntax now but my code is structural so created several objects of the ring oscillator attached together by SIGNAL lines. Then in assignment editor i found pins assigned... so where exactly can a do position fixing??? - - - Updated - - - . is it a material (for the tool or...
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    Ring oscillator design

    Thanks, i got it now. Do u have any ideal as to forcing split on ring oscillator as mrflibble suggested? How is this constraint done in VHDL???
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    Ring oscillator design

    Thanks FVM, just answered that! - - - Updated - - - Thanks man... got those block starring at me... didn't know i needed to double click. Attached is what it looks like. Pls assess.
  8. G

    Ring oscillator design

    Thank you.. i got it now, i appreciate ur post. But do you know how to force a compiler from optimizing a design on the Quartus II software??? Or is there a Reserved word in VHDL that could do that?
  9. G

    Ring oscillator design

    Thanks for the quick one... but i like to know if that code is VHDL, i would prefer VHDL. Also what kind of FF? +++ Slap on an inverter what does it mean???
  10. G

    Ring oscillator design

    Thanks for the break down but pls throw more light (enlighten) on using FF as a clock divider. How is it done? Kindly give a sketch of design and attach to your comment. Am also experiencing a similar challenge. - - - Updated - - - Am also experiencing a similar challenge, but unfortunately i...
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