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how to write a verilog wraper for vhdl design
finally it works, i tried starting a new fresh project and using ise9.2 with the latest sp. i still dont know why it didn´t work before though. ¨
anyway, thanks for the help.
can we mix vhdl and verilog in xst
aha, i see. oh and bythe way the property i set was "verilog include directories" under synthesis- properties.
Nope, didn´t help.
but it works if i comment the line " count4 counter(.CLK(clk), .Q(q)); " that instantiates the vhdl block :cry:
rpsyscore_api.v
ok, that worked, but not when i have this:
module top `include "rpsyscore_api.v"
wire clk;
wire [3:0] q;
wire [3:0] icount;
count4 counter(.clk(clk), .Q(q));
assign icount = ~q;
endmodule
where rpsyscore_api.v specifies the ports and the "verilog...
include vhdl
im using xilinx ise 9.1
have tried using the verilog file as top and simlpy instantiate the vhdl as a module,
example:
u_l user_l(
. clk(usr_clk),
.addr(ht_wr_addr)
);
but it says unexpected error when i run synthesis.
verilog include
is there an easy way to put a design in vhdl inside a verilog design?
i have a nice dynamic verilog file with port declarations towards the external hw, but i want to write my own logic in vhdl. not so familiar with verilog yet.
can i write some kind of wrapper for the vhdl...
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