Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
My sub module will be as follows
Module sub(input clk, input rst, output reg a[0:10]);
reg i;
always @(posedge clk)
begin
for (i=0;i<10;i=i+1)
begin
a[i]=1’b0;
end
end
endmodule
My aim is to initialize an array to zero by using submodule. But I am not able to pass the array since it...
How can I instantiate an array in verilog?
For example, I Have an array a[0:10] in my top module.I want to pass this a[0:10] into another submodule. How it is possible?
I tried like this but showing error.
module top
{
input clk,
input rst
};
wire a[0:10];
sub dut( . clk(clk)...
During integration of different parts of my digital circuit,the output voltage of one section [which needs to drive an nmos] is dropping from1.8v to 0.4v.How can I avoid this?
I have a basic doubt about clock skew.Consider during manufacturing time ,I have optimized my design for minimum clock skew.Is there any chance for occurring the skew again in real time working of the ASIC?
Is there a way to simulate a digital to analog converter in ModelSim????? I have my Verilog code that produces the 16 bit input to a DAC . It would be really nice if I could somehow see the analog waveform in simulation...
I have written the following verilog codes.....The first one will execute in one clock cycle......But due to multiple assignments of variable ,the second code is not executing in one clock cycle.....Can anyone suggest any method so that the second code also will execute fully in one clock...
In my design all the iterations of for loop is executing in one clock edge....
I want a for loop which will execute one iteration in one clock edge...That means in first rising edge of clock,it should execute first iteration of for loop.In second rising edge of clock,it should execute 2nd...
Actually above code is only a sample...I want to include a block of
statements in each iteration that i want to execute sequentially in each
clock cycle..If i go for state machine i want to replicate my code for
each state and code length become very large...Thats why i am asking
about for...
ok..then how can i modify the above program so that the for loop will
execute only one iteration for each clock.....
PLZ help me....thanks for ur reply
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
