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Recent content by globaleda

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    DOES CMOS IMAGE SENSOR NEED SPECIAL TECHNOLOGY?

    Yibin, I think you are right. Using standard proecss you cannot get high performance imager, especially with 0.18um or less. By the way, do you know any job opportunities in CMOS image sensor design? I'll appreciate your information. Thanks in advance! global
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    DOES CMOS IMAGE SENSOR NEED SPECIAL TECHNOLOGY?

    Of course you can use standard CMOS process to do imager sensor. However, optimized process gives you better performance. I have done several chips of CMOS image senosr using standard tsmc process. All work successfully. By the way, are you still interested in working on this topic?
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    Why Vth changes with transistor size and bias condition

    channel length modulation vth if you open a model file from MOSIS test results, you will see Vth depends on transisotor size. It's just not included in our simple hand calculation model.
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    Analysing waveforms using spectre.

    I use virtuoso analog env. It has a integrated calculator which can do a lot of analysis functions. I doubt if your env has something similiar.
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    Why using transistor sizes larger than the minimum length?

    Re: transistor size 1. for better matching 2. for smaller lamda: lamda is proportional to 1/L. 3. for smaller Id current
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    capacitive load vs. resistive load

    some times capacitive load are used to avoid DC current, thus lower down the power.
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    Cadence simulation problem

    I'm interested too. I normally simulate the digital part seperated using synopsis. You can use ideal digital model from ahdl library to speed up the mixed-signal simu. However, I guess there are better solutions.
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    How to size the pMOS and nMOS in NOR NAND XNOR gates?

    nor pmos nmos I think it depends on 1. the load. you need large mos to drive large cap load. if load is minimum, you can use minimum mos. 2. the drive capability of your previous stage. it should be able to drive this gate as a load at a given speed. be careful that your previous stage may...
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    Analog IC Design Prospective

    we have two fists, analog and digital. both of them are necessary in fighting. it is meaning less to discuss if analog will 'die'. the only difference is if the demand of analog designers is larger or smaller than the schools can provide.
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    How to cancel offset in OpAmp?

    Re: offset cancellation I think it mainly depends on your opamp operates continuously or clocked. If it's clocked, you can used switch-cap feedback to cancel the offset successfully. It it's continuous, it is much harder. Following are some methods I can think of, 1. better matching in layout...
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    What is the future for CMOS Analog IC Designers ?

    how about CMOS image sensors? I saw a fast growing market these five years.
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    VDD for TSMC 0.25u CMOS Technology

    yes. 2.5v is the standard and suggested voltage. however, you may choose multiple power supplies for different parts of your circuits - for lowering down the total power, or get some flexibility. Normally you can use from 2.5v-Vth to 2.5v+Vth. I've tried this in 3.3v process and looks like it...

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