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hello all,
many of u might working on UMC 65nm. i am working on current mode signaling scheme, trying to see the effect of scaling in CMS. for that i have to knw coupling capacitance and resistance for global wire(highest metal line that can be used for clock destribution). in my place QRC is...
i also need the same. can u plzz send girish_nayak002@yahoo.co.in
---------- Post added at 14:12 ---------- Previous post was at 13:48 ----------
i also nee plzz send me also
Best Minimum delay for 2x1 mux using transmission delay(65nm node)
hello all,
i designed 2x1 mux using transmission gate in 65nm node. i am getting 40ps delay from mux. any one can suggest me method to reduce delay. i knw the delay depends upon the o/p and i/p load. i want to knw any one have...
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