Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by gireeshkkm

  1. G

    [PrimeTime] List of all registers

    I think you can try like get_cells -of_object <ref_names of registers> * get_cells -filter {is_sequential == "TRUE"} *
  2. G

    [SOLVED] What does mean ARM hardening?

    For example, you are designing an SOC based on ARM. ARM will provide you RTL for their processor. Assume that you are using TSMC library. Then you will synthesis this ARM processor RTL and other part of your SOC using TSMC library (Followed by PnR). The process of converting ARM RTL to...
  3. G

    What is the difference between get_timing_path and report_timing

    Generally get_timing_path is used for writing scripts. For example, if you want to get name of endpoints of all violating paths... report_timing can be used as a general purpose command.
  4. G

    SDF and SPEF usage with PT

    Do we need both SDF file and SPEF file for static timing analysis using Prime Time ? or is that enough if we read either one of them for static timing analysis using PT ? either SDF or SPEF+.lib is enough Can backend tools (like IC compiler) write out both SDF and SPEF ? Yes For different...
  5. G

    diffrence between spare cell and unconnected cell

    Spare cells input must be tied to HIGH or LOW. And it is used for ECO. Unconnected cells shouldn't be their in your design
  6. G

    Isolated Via Violations

    Why we are fixing isolated via violations is ASIC design?

Part and Inventory Search

Back
Top