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Recent content by ghattasak

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    Strain Gages output calculation

    Hello Guys, i have the following sensor a general purpose strain gages from Vishay; EA-06-125BT-120/LE but I do not understand how the sensor operates, does it outputs a specific voltage level dependent on the measured temperature ? or vibration? and as for the output pins it is stated on...
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    VHDL coding style for better performance and timing constraints

    oh ok thank you :D I will recheck the tutorial and specify them a multi-cycle then my inputs are 64 - 2bit signals a start signal and a reset I did not check how will my input get in as it's a very large and annoying design part since my design is serial with parallel circuits I will need to...
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    VHDL coding style for better performance and timing constraints

    hello guys I am working on a project: block matching using online adders and Sum of absolute difference computation I have written the VHDL code and run the project fully on 3.8ns on altera cyclone V but i did not put any constraint on my input and output yet I would like you if possible to...
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    android programing problem with ListAdapter

    import java.util.ArrayList; import java.util.List; import android.os.Bundle; import android.provider.ContactsContract; import android.provider.ContactsContract.PhoneLookup; import android.app.Activity; import android.app.ListActivity; import android.content.Context; import...
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    test if set in vhdl different implementation

    done_sort <= '1' when done_arr =((others => '1')) else '0'; can i write it like this ? supposedly done_arr is an array of 0 to M and i want it to varry depending on M and not set up like a 1000 1's - - - Updated - - - @TrickyDicky i am using the and_reduce now to check for the results thank...
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    test if set in vhdl different implementation

    it will cost me more hardware right ? if i have lets say an array of 1000
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    test if set in vhdl different implementation

    if i have a array of 0 to M ot std_logic in vhdl and i want to test if it is set having all bits 1, is it advised to use "and gate" or should i use an if statement. what is the difference in hardware?
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    vhdl problem with latches from incomplete statements

    hello i am having a problem with the vhdl code i have tried assigning all wires to a value but couldnt solve the latche error can anyone help me and clarfiy the problem? and how can it be solved? WARNING:Xst:737 - Found 1-bit latch for signal <ctr_rst>. Latches may be generated from incomplete...
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    opinion for design result

    hello i implemented a sorting networking in the fpga it can be run at 200mhz and can fit 2930 8 bits number the chip used is virtex 4 xc4vlx40 -12 ff668 do you think this a good result stating that the purpose is to put in as much data as possible at a good sorting speed
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    [SOLVED] microblaze question and clarification

    oh ok thank you :D that was great
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    [SOLVED] microblaze question and clarification

    hello i am trying to implement ethernet on xilinx spartan 3e starter i have noticed two options the use of microblaze and the use of a vhdl core what is the difference? i do not really understand the advantages microblaze gives to make it and easy implementation since the mac core can be...
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    finding solution for Not So Flat After All Problem code: ANARC09C

    hello does anyone have a working code for the https://www.spoj.com/problems/ANARC09C/ problem in c or c++ so i can check/compare please i cant find any on the web and im stuck
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    xilinx rocket io learning materials

    yes but cant i connect the wires to the sata interface of the mgts ? ill build an intermediate board with wires connected - - - Updated - - - then i can make a gigabit phy in the fpga
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    xilinx rocket io learning materials

    ok i got myself a network card supporting 1gbps i will try to implement this on the virtex 2 pro digilent board :D
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    xilinx rocket io learning materials

    thank you :D and sorry for the hard time that clarified alot
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