Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by gharuda

  1. G

    which netlist is compared against the final GDS for LVS

    GDS is format which is given to the fabricator. LVS means layout versus schematic , netlist is genrated from the layout and netlist generated from the schemetic is compared. gds is not compared with lvs
  2. G

    how to use nested always?

    always cannot be nested in verilog. always staements are processed paralling in hdl two or more always statement can be used in a program to achieve the function .
  3. G

    Can't by-pass Bios (can't even see my bios)

    try delete key it will work
  4. G

    The following generated clock has no path to its masterclock

    Re: The following generated clock has no path to its masterc I am sorry buddy I didn't get grst to be reset signal (which is similar to clock gclk) just went through your coding first time but still I didn"t get this part in your code is clk_gen which is declared to be wire while in your...
  5. G

    The following generated clock has no path to its masterclock

    Re: The following generated clock has no path to its masterc I believe you are using two clocks 1) gclk 2) grst from where these clock signal are generated. for eg if your are going to implement the design on a FPGA board, which has a clock...
  6. G

    nmos bulk in cadence layout

    In your layout why the transistor are in different orientation use only (horizontal) or use only (vertical). avoid using both.
  7. G

    synopsys design constraint

    was the code synthesised before applying constraints
  8. G

    why change in technology from 90 nm to 65 nm

    check out this PDF https://www.google.co.in/url?sa=t&source=web&ct=res&cd=6&ved=0CBcQFjAF&url=http%3A%2F%2Fdigilander.libero.it%2Fkayk%2FApprofondimenti%2FTerahertz.pdf&rct=j&q=.35um%2C90nm%2C+35nm+technology&ei=IQBpS5yeLpLm7AP16_TGBg&usg=AFQjCNEnFfUefYYbsMG9VIEvzMUfyCZzsQ
  9. G

    Where can I find the list of companies doing ASIC? For job

    Re: Where can I find the list of companies doing ASIC? go for Indian semiconductor association https://www.isaonline.org/index.php/membership-/isa-member-list-.html Added after 30 seconds: go for Indian semiconductor association...
  10. G

    What is the meaning of the bird's beak?

    bird's beak.. you got my name wrong . you find the required contents in the book VLSI fabrication principles by s.k.ghandhi i don't have a soft copy of the book.
  11. G

    Generating a new .sdb file for the 45-nm library

    Re: Missing .sdb file sorry its not file is a format .sdb is standard database format and used for symbol libraries. try reading the tsmc90ghp.sdb in the dc shell may be it could help
  12. G

    Generating a new .sdb file for the 45-nm library

    sdb slib synopsys library its stands for standard database file it depends upon the technology. and usually given by the EDA tool vendor
  13. G

    How to write the power-up block?

    putting power in sensitive list a power up block could be written. use either level or edge depending upon requirement
  14. G

    What is the meaning of the bird's beak?

    Re: bird's beak.. Isolation between mos device in any microcircuit is obtained by LOCOS technique. the problem arsing during this process, the oxidation of silicon slightly extents under the nitride. the second problem comes due to large mismatch in the thermal expansion coefficients of...
  15. G

    Race condition check in Verilog

    verilog schedule 2 event at same time it depends upon the assignment statement your using blocking "=+ or non blocking statements "<=". their is inertial and transient delay while a expression is evaluated and assigned to a LHS variable. if u don't specify any delay then inertial delay is...
See more

Part and Inventory Search

Back
Top