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Recent content by GertDalPozzo

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    Delay generator on Altera FPGA

    fpga delay generator Hi everybody, I got some problems during the implemenation of a simple delay generator on Stratix II. I realized a shift-register ram based with many taps, so I could select the desired delay for the circuit. After implementation I analyzed the behaviour giving a sine wave...
  2. G

    Buffer for sample rate conversion

    That's fine! Thanx Gert
  3. G

    Buffer for sample rate conversion

    Yes, it was useful. But the only code in the pdf is about a single clock FIFO while I need a dual-clock one, 'cause the concept is quite different and more complex.
  4. G

    Buffer for sample rate conversion

    Thank you very much Zerox100! In the web I found only descriptions of how to use Dual-Clock FIFO megafunctions by altera, but I'd like to have VHDL code for that function, otherwise I can't really understand the behaviour of the model. If you could upload it or post a link, I'd be really...
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    Buffer for sample rate conversion

    I mean a module that can translate the sample rate from 200 MHz to 150 MHz. I have a data stream that changes every 10 ns but it is sampled at 200 MHz; I need a module that gives on output that data stream sampled at 150 MHz. Thanx
  6. G

    Buffer for sample rate conversion

    Hi everyone, could someone give me the VHDL code of a generic buffer for sample rate conversion? e.g. from 150 MHz to 200 MHz. Hope that someone could help me. Thanks! Gert
  7. G

    Help me translate this Verilog code to VHDL

    Re: verilog to vhdl Do you need a behavioral description or it's good for you also a structural one?
  8. G

    details of NiosII evaluation board 1c12

    Maybe here you can find what you are looking for! http://www.a.ltera.com/support/ip/processors/kits/ips-nios2-dev-kits.html
  9. G

    Use of functions,procedures in vhdl

    functions in vhdl Are you sure? I read you can use them only inside processes. From "VHDL Cookbook" by Ashenden: "We can write a procedure declaration in the declarative part of an architecture body or a process. If a procedure is included in an architecture body’s declarative part, it can be...
  10. G

    Use of functions,procedures in vhdl

    procedure vhdl >1. apart from the compactness of the program,will hardware become less or reduce ?? No hardware reduction...nothing that you can't also do without using functions and procedures. >2. Can we say that using procedures,packages,functions as good programming in vhdl?? What do you...
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    Use of functions,procedures in vhdl

    vhdl procedure I never used functions and procedures in VHDL programming, cause I don't like them very much. You're right when you say that it's more or less like C language, but you always have to think that you are using a hardware description language (not a programming language), otherwise...
  12. G

    Stupid question about FIR filters

    Hi All, is there a relationship (a simple formula) between FIR filter order (number of taps) and passband width? Because I know that if the passband is narrow I need an higher number of taps, but I don't know if this relationship is linear or if there is a way to determine at least the minimum...
  13. G

    Low-cost vs. high-end FPGA

    Thank you very much Echo! So, do you think I can design my architecture (using VHDL) with one of the software available (ISE or Quartus) and then try to fit into a low-cost package and simulate it? If the performances are right for my application I can choose a low-cost FPGA, otherwise I will...
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    Low-cost vs. high-end FPGA

    Hi All, someone could tell me the main differences between low-cost FPGAs and high-end ones? (i.e. Spartan vs Virtex for Xilinx and Cyclone vs Stratix for Altera). Because I had a look at many datasheets and I didn't see so much differences, excluding the price! Considering the same number of...
  15. G

    Algorithm for positioning of echo cancellation windows

    Dear All, I'd like to know any algorithm for positioning the cancellation windows inside the research window of an echo canceller. The purpose is to achieve the highest energy of echo signal inside each sub-window, but I don't know any sub-optimal algo to do this! Thanks for helping me! Gert
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