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Recent content by genmadow

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    FFT VHDL code to be synthesizable in ASIC...

    Dear Iamventure, Can you explain further in more details how you ported your design using Synopsys DC? I mean if you have a VHDL netlist synthesiszed using Xilinx ISE, how can I import it in Synopsys DC?, and how can I make the mapping proces between Xilinx cells and ASIC cells using Synopsys...
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    FFT VHDL code to be synthesizable in ASIC...

    Dear PINI_1 Thanks for reply, I need fixed point FFT, I don't know whether this code support the fixed point or not, I will take a look; Thanks for your help ---------- Post added at 23:55 ---------- Previous post was at 23:52 ---------- Dear Iamventure, Thanks for reply, I think it is a good...
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    FFT VHDL code to be synthesizable in ASIC...

    Dear All, I want some help in obtaining VHDL code for fft to be synthesizable in ASIC, I saw XILNIX matlab system generator block for FFT but it was targeting FPGA but I'm targeting ASIC as I said, I'm using Leonardo tool for synthesis, Please anybody helps.. Thanks...
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    How to convert edif or vhdl netlist to spice netlist?

    netlist conversion hi.. can anybody help me in how to convert edif or vhdl netlist to spice netlist? thanx
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    Help me to write a VHDL code defining a 2 dimensional matrix (16 * 16 matrix)

    Re: vhdl problem thnx for peply.. i want to use this matrix as 16*16 rom which is used to store units of 8 bits each(the elemnts of the matrix)
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    Help me to write a VHDL code defining a 2 dimensional matrix (16 * 16 matrix)

    hi all, i want to write vhdl code defining a 2 dimensional matrix (16 * 16 matrix) but every element in this matrix is an array of 8 ... and how to write this code in entity...? thanx
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    problem in defining 2 dimenisional array in vhdl

    defining matrix array in vhdl hi all, i want to write vhdl code defining a 2 dimensional matrix (16 * 16 matrix) but every element in this matrix is an array of 8 ... and how to write this code in entity...? thanx
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    asking for *.tdb files

    hi i'm using ledit in automated routing of digital circuits...i'm using AMS c35_corelib. when using ledit spr it asks me for the library in *.tdb format to make cell mapping...can any body help me in obtaining this *.tdb file..
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    asking about xilinx area optimization

    i'm working on xilinx ise v6 ...i'm using achain of inverters..the nomber of inveters is even..but ise collapse all inverters and delete them.. how can i enforce ise to keep this inverters as they are... i know there is a way on constraints..but i don't know this..
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    modelsim memory limitation

    hi, i'm working on modelsim but when i tried to load my design this message appeared " The ModelSim Evaluation memory limitation has been reached".. how can i overcome this problem?? please advise>>
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    Problem with converting design into ASIC in LEDIT

    Re: Asking about LEDIT hi, i have my edif file exported from lionardospectrum using the sample technology file SCL05u... when i used ledit place and route i couldn't make mapping from my cell names into .tdb(tanner database) file... can any body help me plz:!::!: thanxxx
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    Problem with converting design into ASIC in LEDIT

    Re: Asking about LEDIT the netlist is in RTL form
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