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Recent content by GDesign

  1. G

    Timing Budgeting between Blocks

    Yes, that is what I am asking. My first enquiry was: "I think that I should change the input/output delay constraints. Am I wrong ?"
  2. G

    Timing Budgeting between Blocks

    Yes, Block1 is a macro(ADC, DAC, CPU, etc).
  3. G

    Timing Budgeting between Blocks

    Hi, many thanks for your reply. Block1 is an external block(macro) that is connected by AXI to Block2. I am in a very early stage of my design and I would like a method to have a first budgeting. Sorry for the confusion. GDesign
  4. G

    Timing Budgeting between Blocks

    Hi, I need to do the following budgeting: Block 1 --------> AXI Stream Interface --------->Block2 At the moment: clock Block1 is 500MHz and input/output delays are set to 50% If I need to increase the clock of Block1, for example to 2GHz, I think that I should change the input/output delay...
  5. G

    Get TLUPLUS from ICT/capTable ?

    Hi, My current work environment is CADENCE, so I have ICT and capTable. I need to setup a SYNOPSYS work environment but I don't have TLUPLUS. I wonder, if it is possible to get TLUPLUS from ICT/capTable. Many thansk for your help, gDesing
  6. G

    MIX Vt cells in clock tree

    Hi, many thanks for your reply. it is a fix due to power issues: doing the swap for some cells I don't see any big worsening regarding timing. Best Regards
  7. G

    MIX Vt cells in clock tree

    Hi, I am working on TSMC 40nm technology. I would like to understand why it is not recommended to mix different Vt cells into clock tree. Many thanks, GDesign
  8. G

    Correct BUMP Pitch to use

    Hi, I am working on TSMC 40nm. I need to use BUMP cells and I would like to get the right bump pitch to use. Inside the BUMP's documentation I read the following differences that determine the "Bump pitch": "On Silicon Dimension" and "Design Dimension" What Are these difference ? Thanks
  9. G

    SPEF to be used for Power Analysis

    Hi All, I am working on 40nm technology. I am using StarXtract to make SPEF files. In this tool it is possible to choose between RC and C extraction. I am wondering what SPEFs is more correct to use inside PrimeRail: SPEF extracted with RC o C ? Thanks
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