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Recent content by gavinsun

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    Query regarding timing from faster to slower clock domain

    Re: Query regarding timing from faster to slower clock domai Hi Jean, I think you are wrong. The tool's behavior is correct. Yes, there are two relations for hold timing check. 4->4 and 2->0. But the most restrictive one is 4->4. hold timing requirement is: data arrival time > data required...
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    Need help in interface in verilog - One Clock Pulse?

    Re: One Clock Pulse? Could you show your interface protocol? such as request, ack,... how they are working?
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    Need help in interface in verilog - One Clock Pulse?

    Re: One Clock Pulse? implementing one level request queue at receving side. ACK = ~Queue_full & REQ; Queue_push = REQ & ACK; Queue_pop = ...
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    How to constraint the PLL when we do STA?

    You mean create clock on pll, set clock source latency for pll output clk or other item???
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    what is useful skew.how will come useful skew?

    Thanks a lot. It is so useful to me.
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    what is diff between Block based STA and path based STA

    Path based STA is broadly used by current STA sign-off tool (Primetime, TimeCraft). Timing constraints will be checked at endpoint of the timing path. the AT of endpoint should less than RT. BLock Based STA: timing constraints will be checked at each node of the timing path. each node own...
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    Flip-Flop resolution time and CDC synchronizer

    cdc synchronizer Hi All, In our previous design(.15um), we use a dedicated CDC synchronizer cell (zpmtffb) as conversion cell, which is composed by two pipe flip flop, the first one is negedge CLK triggered and the second one is posedge CLK triggered. It has been proved by...
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