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Recent content by GaryHan

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    Berkeley EECS140,240,247 Classes

    Is there anyway to download the videos to my computer?
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    What is "ROOM" in protelDXP? Can you explain it?

    I have deleted the rooms that way. But when use zoom/all, the display area is the board plus the rooms' area. How can make this display normal? Added after 7 minutes: When delete the rooms, sch update pcb always say add rooms that have just deleted? How can you do? Or is it very important...
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    What is "ROOM" in protelDXP? Can you explain it?

    Where can i turn this option off and remove the rooms?
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    What is "ROOM" in protelDXP? Can you explain it?

    I have not used the ROOM in protel 99SE and DXP. But when i update PCB from sch in DXP, there are many ROOMs in the PCB layout. It seems that i do not delete them because errors will be generated when update PCB. Who can explain the usages and meaning of ROOM? How can i deal with them? THX!!!
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    Pipeline ADC design's puzzle

    I am designing a 8bit 100MHz Pipeline ADC, and the result puzzled me. The structure is 1.5bit/stage *5 + 3bit/last stage. The result is that 1Lsb is always wrong. Can someone give some advise ? Or point some key notation? Additions: In this design, there are a S/H circuit, gain stage(include...
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    One question of hspice/spectre simulation?

    How to build a ideal voltage controlled capacitor model using Spectre verilog or Verilog A? Can you describe it in detail? Thx a lot!
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    One question of hspice/spectre simulation?

    When I do trans simulation, i wann to change a cap value during the simulation, not restart the simulation, but in the simulation to see the parameter of the cap influence the result? How can i do using the hspice or spectre in the analog artist? Thx 8) Maybe I don't speak it clearly, I give...

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