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Hi speedEC,
Did you find a solution to this problem. I am trying to do the same thing. If you have made the footprint for expresspcb can you please share it with me
I think i am in the wrong forum full of egoistic people.... You what what ever you assume but frankly i dont have time to deal with your ego here....u r free to write what ever you want but that is just useless....
Actually that is not my misunderstanding... I am trying to say that thats why i cannot pipe line....
---------- Post added at 11:03 ---------- Previous post was at 10:58 ----------
ok... i think i will ask you a question and tell me how will you pipeline in that case.
Suppose i have a 4...
You are right but then i cannot pipeline the data here because i need the data to be constant for next 16 cycles in order to parse it bit by bit. If i take the next data into same register then that will break my operation. In pipe lining you assume that there are different operations to be done...
By ports i mean i cannot stop data from coming. I have to process it.There is no buffer. So no imagine that i have 16 input ports. From all the ports i am getting data on each clock. On each clock i must see what all ports are carrying valid data and write it them to fifo's. Now to implement...
Ok well i am sorry for the wrong info. Actually there are 16 data ports on left hand side not buffers. So now on each clock cycle there will be data (valid or invalid denoted by msb bit of data) on 16 ports and i need to put this data into the fifos on right hand side. The writing in fifo is...
"I understand that the whole idea of getting the indexes of ones is that you then have the indexes of ones " -- I dont know what you mean by this.
"Is this going to be synthesized? Or is it just for simulation?" -- I said i want to design a combinatorial circuit. Why would i write a...
for input_a output will be 64'hfedc_ba98_7654_3210
for input_b output will be 64'h0000_0000_0000_0000
For input_c output will be 64'h0000_0000_0000_0000 .. i will qualify the lsb nibble 0 by looking at the input
The whole idea is to get the indexes of ones. Now since the no of ones can max be...
Hello lucbra.
Thanks for your reply..
I tried searching a lot and i did not found any such solution. Can you please direct me to any such thread.
Thanks
I want to design a combinatorial circuit for an fpga which will count the position of ones in a 16 bit vector.
eg1 if vector is 16'b0000_0000_0011_0101 then output should be
64'h0000_0000_0000_5420
eg2 if vector is 16'b0000_1010_0000_1010 then output should be
64'h0000_0000_0000_b931.
Please...
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