Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
i am doing a project on generation of true random numbers in FPGA, and my program was running fine with no errors in Modelsim but when i loaded the same in xilinx the below error is shown. but the problem is there is no line 62.
"F:/M-TECH/s4/finals/all latest working/topp/topp/ring1.vhd" Line...
can u plz help me in coding a ring oscillator in vhdl?my project is generation of true random numbers in fpga.its 1st stage is ring oscillator plz help
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.