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Recent content by galant

  1. G

    why do we need SystemC language?

    Actually systemc mostly used for system level verification now although there are some eda tools that can synthesis systemc into hdl.
  2. G

    How to do LEC in RTL vs gating-clock netlist(power compiler)

    set flatten model verplex Is it reasonal that the result is different between the dynamic gate-level simulation and the static formal check? In some degree, i think, the answer should be yes.
  3. G

    what is hot-topic in digital design now?

    In my eyes, although Soc is very hot, many students think it as same as ASIC.So most of real soc products are under way.
  4. G

    Reading values from file in SystemC

    In systemc, you can use "openfile(), readfile()..." as well as you do in C/C++.
  5. G

    Hoe to use systemC with spice designs

    I think you can run digital model writed by systemc and anlog model by spice mixed simulation in some simulation tools such as cadence nc and ultrasim.
  6. G

    what is the different of simulator and emulator?

    One of difference between simulator and emulator is the simulation speed. Because the emulator have the simulation acceleration feature, its simulation speed is much higher than simulator's.
  7. G

    Anyone use MATLAB in VLSI designing

    matlab code for vlsi Basicly matlab is for algorithm simulation. But now Matlab integrated some RTL co-simulation and FPGA core co-sim functions. It's sounds good. But is there anyone convert Matlab model to RTL automaticlly?:0
  8. G

    Some question about using ncsim ?

    using ncsim with cygwin Oh,you may get the help from Cadence CRC. We use ncsim only in Unix platform.
  9. G

    What is the best way to reduce power for low power ASIC?

    Re: LOW POWER ASIC In my opinion , the system level architecture design is more important than the EDA tools. Most of eda companies are always boosting their products .
  10. G

    IC design lission from Berkeley

    We could not get any course material from this website. :(
  11. G

    What does ASIC exactly mean?

    Re: what is ASIC SOC=ASIC+CPU+DSP+BUS....?
  12. G

    The significance of wire load and speed grade

    Re: wire load significance Wire load model is one of basic features of the synthesis and PKS tools now.
  13. G

    Synopsys Common Licensing

    synopsys.common.licensing.scl Oh, is the synopsys license manager different with cadence? If yes, you need only install the flexm license manager.
  14. G

    Looking for website with tutorials about P&R

    Re: Help on P&R There are many books of P&R in this server. I have download a book named "layout basic". It's very useful, I think.
  15. G

    Whats partition in SOC Encounter ?

    Re: [HELP] SOC Encounter SOC Encouter is better for hierarchical p&r. And I heared that it is very fast.At same time it is very expensive.:(
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