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Recent content by gahelton

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    Watchdog timers and FPGA designs

    First, I'm sorry if this is a re-hash of any existing posts, many of which I have read. But I think that a watchdog timer would be useful for my design. This one seems relevant. https://www.edaboard.com/threads/watchdog-reset-for-fpga-designs.247625/ The way that a watchdog would have to work...
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    FPGA timing, signaling between processes

    Thank you for the replies. I will use single pulse, positive edge aligned for both signals as shown. As far as the "do_something_complete" feedback signal from Process B to Process A, Process B may be many clock cycles long (like a 32 bit multiply or divide). The calling process (Process A)...
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    FPGA timing, signaling between processes

    This question relates to sending signals between two processes, and timing concerns. I have a system where Process A sends a signal to Process B. The signal is one clock cycle long beginning on the positive edge. Process B needs to capture this signal, do the requested logic, then signal a...
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    VHDL abs() function speed

    Thanks for the replies everyone. The timing violations (as reported) were primarily in the division component, and they were register to register violations due to the ripple effect of the subtraction portion (as best as I could tell). There were no reported violations in the abs() function. The...
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    VHDL abs() function speed

    I am having problems meeting timing requirements for my FPGA design (VHDL). According to the timing reports, the bulk of the timing errors are related to math functions in my ALU. The math functions are 32 by 32 bit with 64 bit temporary values for the multiplier and divider (there is no HW...
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    SDC file for clock creation

    Hi Kaz1, Thank you for the reply. I tried the "derive_pll_clocks" option with no success. It doesn't give me a warning, but it doesn't work either. ==================================================================== This was the sdc file. set sdc_version 1.7 set_time_format -unit ns...
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    SDC file for clock creation

    I'm sorry, but I'm about at my wits end. I have been trying to create clocks for an FPGA design so that I can verify timing constraints. I've tried some many iterations and followed examples with very limited success. Below is a block diagram for my system. Ultimately, I need to create a clock...
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