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--excuse me data is equal=3 I MISTAKE THERE.
my problem is I cant see type of when( 2 and 3) on ouput on hardware(fpga board) I only see type of when 1
and other problem I assign led<=conv_std_logic_vector(data,6) but I CANT see it on out put on board(by led's) ( my delay is equal 1s)
how can I...
HI TO ALL.
in the first:
I write this vhdl code for fpga with xin=10mhz
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use...
HI to all.
can you help me?
I design one of circuit that work at 4_5 GHZ with 2-2.5 GHZ INPUT.
HOW CAN I calculated of devices?
how much C6,c3=? c4=? R4,R5,R6=? AND R11,R12=? WITH vcc=9v and F=2 to 2.5 GHZ INPUT AND OUPUT?
AND IF WE OUTPUT FREQ= 4 TO 5 GHZ WITH 2 TO 2.5 GHZ INPUT
how much...
hi,I have one problem in ISE13 SIMULATION.
when I want to make test bench my project the ISE has this error:
ERROR:Simulator:702 - Can not find design unit work.si4136test in library work located at isim/work
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