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Recent content by FuzzySNR

  1. FuzzySNR

    DSP48E1 - Warning: OPMODE Input Warning

    No unfortunately not, the user edited rtl code generated from the high level synthseis tool goes that deep in the hierarchy as of the translated c functions of the user code.
  2. FuzzySNR

    DSP48E1 - Warning: OPMODE Input Warning

    Thanx, I'm aware of this thread but unfortunately noone has come up with a solution yet.
  3. FuzzySNR

    DSP48E1 - Warning: OPMODE Input Warning

    I get the following warning during co-simulation of my design in Vivado HLS 2016.4: Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL 000 to DSP48E1 instance is invalid. Time: 138265 ns Iteration: 11 Process...
  4. FuzzySNR

    two questions in matlab

    1. Look for Switch under Signal routing 2. Look for Subsystem under Commonly used blocks
  5. FuzzySNR

    problem in matlab simulink

    It's clear enough, don't think a snapshot is necessary! Go to simulink library and search for: 1. data type conversion 2. SimElectronics and have a look at the sources.
  6. FuzzySNR

    problem in matlab simulink

    Obviously you can't! Pulse generator signal output type is incompatible with CMOS Buffer and D-FF. For the D-FF you can insert a data type conversion block. For the CMOS buffer you have to use sources from the SimElectronics toolbox only.
  7. FuzzySNR

    What is for CLKIN_IBUFG_OUT?

    CLKIN_IBUFG_OUT is simply a buffered form of CLKIN_IN.
  8. FuzzySNR

    What is for CLKIN_IBUFG_OUT?

    There is a nice discussion here, have a look: http://forums.xilinx.com/t5/New-Users-Forum/difference-between-CLKIN-IBUFG-OUT-and-CLK0-OUT/td-p/310795
  9. FuzzySNR

    Linux kernel build problem in Xilinx ML605

    Oohh, I see, yes I could do that. I thought you meant to check SW wise. I've fiddled with chipscope couple of times, so I might as well try it. Thinking twice, since I've included an MDM module in MB, I could use mb-gdb to dump register contents (saves me from inserting chipscope). Follows...
  10. FuzzySNR

    Linux kernel build problem in Xilinx ML605

    OK, for the Kernel: git clone https://github.com/Xilinx/linux-xlnx.git git checkout xilinx_v3.0 for the GNU toolchain: git clone git://git.xilinx.com/xldk/microblaze_v2.0_le.git for the device-tree: git clone git://git.xilinx.com/device-tree.git git checkout xilinx-3.0-kernel I've got no...
  11. FuzzySNR

    Linux kernel build problem in Xilinx ML605

    Common people...Am dying here!!!
  12. FuzzySNR

    Linux kernel build problem in Xilinx ML605

    OK, I had some progress at last... I cloned version tagged xilinx_v3.0, configured it according to my .dts file, used microblaze_v2.0_le toolchain and finally managed to build the kernel image successfully! Now, the bad news...I connect and download the kernel to microblaze but when I issue...
  13. FuzzySNR

    simple calculator vhdl code

    hmmmm that's your friend's code ah? http://esd.cs.ucr.edu/labs/tutorial/gcd2.vhd Don't really think so...You better start writing YOUR OWN code! When you do so, come back and we might help you then!
  14. FuzzySNR

    simple calculator vhdl code

    Guy, post your code so far and and we will help guy.
  15. FuzzySNR

    Linux kernel build problem in Xilinx ML605

    I see. Any ideas how to "adjust" the microblaze configuration or the make .config file to get past these errors?

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