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No unfortunately not, the user edited rtl code generated from the high level synthseis tool goes that deep in the hierarchy as of the translated c functions of the user code.
I get the following warning during co-simulation of my design in Vivado HLS 2016.4:
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL 000 to DSP48E1 instance is invalid.
Time: 138265 ns Iteration: 11 Process...
It's clear enough, don't think a snapshot is necessary! Go to simulink library and search for: 1. data type conversion 2. SimElectronics and have a look at the sources.
Obviously you can't! Pulse generator signal output type is incompatible with CMOS Buffer and D-FF. For the D-FF you can insert a data type conversion block. For the CMOS buffer you have to use sources from the SimElectronics toolbox only.
Oohh, I see, yes I could do that. I thought you meant to check SW wise.
I've fiddled with chipscope couple of times, so I might as well try it.
Thinking twice, since I've included an MDM module in MB, I could use mb-gdb to dump register contents (saves me from inserting chipscope).
Follows...
OK,
for the Kernel:
git clone https://github.com/Xilinx/linux-xlnx.git
git checkout xilinx_v3.0
for the GNU toolchain:
git clone git://git.xilinx.com/xldk/microblaze_v2.0_le.git
for the device-tree:
git clone git://git.xilinx.com/device-tree.git
git checkout xilinx-3.0-kernel
I've got no...
OK, I had some progress at last...
I cloned version tagged xilinx_v3.0, configured it according to my .dts file, used microblaze_v2.0_le toolchain and finally managed to build the kernel image successfully!
Now, the bad news...I connect and download the kernel to microblaze but when I issue...
hmmmm that's your friend's code ah? http://esd.cs.ucr.edu/labs/tutorial/gcd2.vhd Don't really think so...You better start writing YOUR OWN code! When you do so, come back and we might help you then!
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