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Recent content by funjoke

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    Writing proposal for performances of non-equilibrium thick body

    shall anybody have the idea of writing proposal of the title of performances of non-equilibrium thick body (Id Vs Vgs)?
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    computer organisation and architecture

    computer organisation and architecture mips
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    computer organisation and architecture

    describe the use of stack ? What are the purpose of j,jal and jr instruction and why are they needed for these purposes respectively . anybody know how to do this question?
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    Check my answer to a process state question

    A photo management program is executed.hence , a new process (namely process P)is created.the program will first copy all new photos from a digital camera before it can perform any operation to the photos.While the program is waiting for the file to be copied,operating system switches the...
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    operating system LINUX help

    i have worked out the code but it got some error can help on / CODE: #include <stdio.h> #include <unistd.h> #include <stdlib.h> #include <string.h> #include <pthread.h> #include <semaphore.h> void *productA(void *arg); void *productB(void *arg); void *productC(void *arg); void...
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    addictive or homogeneous

    1)y(n)=x^2(n)/x(n-2) 2)y(n)=x(n)+x*(n-2) prove whether the system is i)additive T(X1(n)+x2(n))=T(X1(n))+T(x2(n)) ii)homogeneous T((x(n))=(T(X(n)) may i know how to solve this question ?
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    single cycle processor mips 32 bit (data memory)verilog

    shall anyone help on test bench of data memory?
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    single cycle processor mips 32 bit (data memory)verilog

    can anybody explain on how this data memory code work on in this single cycle mips ?
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    single cycle processor mips 32 bit (data memory)verilog

    i already edited my code for the data memory ,now i facing error with this line assign address_select = (address[31:7] == BASE_ADDRESS); code: module mem32(clk, mem_read, mem_write, address, data_in, data_out); input clk, mem_write; input [31:0] address, data_in; output [31:0]...
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    single cycle processor mips 32 bit (data memory)verilog

    //synthesis translate_off $display($time, " rom32 error: unaligned address %d", address); //synthesis translate_on i feel this code have some problem on it ...i dun understand why need display ....can anybody helping in making this code more efficient
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    single cycle processor mips 32 bit (data memory)verilog

    initial begin for (i=0; i<7; i=i+1) mem_array[i] = i; end THIS PART NEED TO ADD A NOT ?
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    single cycle processor mips 32 bit (data memory)verilog

    $synthesis translate_off and translate_on($time, " rom32 error: unaligned address %d", address); u sure this line is correct by replacing this ? what does synthesis translate_off and on means ?
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    single cycle processor mips 32 bit (data memory)verilog

    $synthesis translate_off and translate_on($time, " rom32 error: unaligned address %d", address); isnt what u mean by replace this ? Added after 2 hours 10 minutes: isnt change the display to synthesis translate_on besides this is that any error that made this code non -synthesizable?
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    single cycle processor mips 32 bit (data memory)verilog

    then in this question is use synthesis translate_on or translate_off?
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    single cycle processor mips 32 bit (data memory)verilog

    $display($time, " rom32 error: unaligned address %d", address); is that any problem with this sentence ?
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