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Recent content by FrenchRiviera

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    Cyclone IV, Nios II, EPCS64

    Thank you ads-ee for answer. With my EPCS device i can boot both the FPGA configuration and Nios II software. I'm using the Quartus 15.0.When i add the EPCS controller, the DATA, DCLK, ASDI, and nCS signals are not exported to Nios entity. This is why in device and pin options, I configured...
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    Cyclone IV, Nios II, EPCS64

    Ok, thank you. I will review the Quartus design configuration, maybe i made a mistake to configure pins between them together.
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    Cyclone IV, Nios II, EPCS64

    Hi again, Just to inform you that i have always the same problem. The behavior doesn't change even if use the alt_write_flash / alt_read_flash functions or alt_epcq_controller_write_block/alt_read_flash functions. The routine that writes when using alt_write_flash is : /* write to flash 32...
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    Cyclone IV, Nios II, EPCS64

    Thank you very much aruipksni for your answer, I will cheek why i have the endian swapped and the bit shift. I let you know. Best regards
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    Cyclone IV, Nios II, EPCS64

    I want just to precise that in debug mode, I can see that the location where I write changed but with wrong values. For example, I'm writing 0x40228f5c to 04FC0000 address, but I can see this : 04FC0000 2E479120 FFFFFFFF FFFFFFFF FFFFFFFF I don't find an explication why. Thanks in advance
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    Cyclone IV, Nios II, EPCS64

    Hi all, I am building a custom system, using an FPGA board with a Nios II processor. I'm using Quartus 15.0 and DE0 NanoBoard( Cyclone IV as FPGA) My application contains: 1. Clock Source 2. Nios II Processor 3. System ID 4. JTAG UART 5. EPCS Serial Flash Controller 6. PIO 7. SDRAM Controller...

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