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Recent content by frankaurora

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    thin film resistor in bipolar process

    Hi Guys, Which foundry provide thin film resistor in their bipolar process? The thin film resistor need to be trimmed by laser to reach 0.1% accuracy. Thanks a lot! Frank.
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    How to check DRC for partial layout by Calibre?

    you should include "EXCLUDE CELL <cell name>" into the drc rules.
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    op amp simulation help

    you should set CM voltage, ie. vdc>0
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    start-up circuit for ptat current

    Could you explain it in detail? Why C provides the startUp current? Thanks.
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    Does hspice save all node voltage by default ?

    it can save all your circuit nodes voltage including out & 2
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    rpolyh - parasitic capacitance of resistors

    rpolyh's cap The parasitic capacitance is formed as poly is top plate and substrate is bottom plate. So the second rpoly resistor with larger area has bigger cap.
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    Why n+ and p+ are used by welltap&#65311;

    the reason is to reduce contact resistor.
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    difference between VDD-GND(+) and GND-VDD(-) in ESD HBM test

    vdd gnd hi,all In one ESD HBM test report,VDD-GND(+) pass 8kV while GND-VDD(-) fail at 4kV; But I think the two test mode have equivalent ESD discharge path and mechanism, and test result should also be the same; anyone have idea about the difference between them? Thanks in...
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    Avoid bit-blast I/O ports on Synopsys synthesis

    bit-blast you could use bus_naming_style =" %s[%d]" to fix it.
  10. F

    [REQ] Astro 2004.06 lab data

    I also need it, could anyone share?
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    who can share me the "Synopsys workshop guide or Lab g

    it's just what i want :)
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    Which IC layout tool is the best ?

    Re: Layout TOOL agree!
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    Anybody has document on ASIC flow with ASTRO

    does anyone post more labs?
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    Error !!! -- >> Comment?? -->> Thanks

    if u use vsin,u can replace it with vsource and try it again
  15. F

    Berkeley EECS140,240,247 Classes

    berkeley video lecture torrent i can not open "http://cmosedu.com/jbaker/courses/courses.htm" too
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