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Hi,
1) Does the calibreview contain your intentional devices and parasitics?
2) Try to delete (save it in another name before) .../template/"cellname".stl. This contains the description of all the ports in your design. It should be regenerate on your next run.
Hope it helps.
Franck
Hi,
If you are running PEX, I guess you also have the Calibre documentation installed.
So search for "calibreview" in the calibre extraction documentation.
Everything is explained there.
Franck.
Hi,
I think you should use the calibreview to do your post layout simulation.
It's one of the output format of PEX.
It's particulary easy to use with a config view.
Franck.
Hi,
Thanks a lot for your help.
How would you place those dummy metal patterns? Interleaved in the transistor? Around the transistor?
Would that help to stack every metals in the unit pattern?
Do you confirm that for a same size of transistor the bigger the conducting/switching region layout is...
Hi,
I'm doing a layout of a power amplifier and I'd like to know if there is any particular techniques (obvious or not) to help heat dissipation. I mean what could I do in the layout of the active part of the PA?
Thanks,
Franck.
Hi,
The main reason you need to think about mask shift is for matching.
45 degree angle for gates is used in digital layout.
You don't really need to take care of matching in digital.
And by the way I don't think a mask shift would be big enough to not process poly over the desired active area...
Re: Standard Cell Layout
Hi,
Really strange question.
A mos is a 4 terminals devices: gate, drain, source and bulk.
What we call "tap" in layout is the bulk connection. It's for that you always have substrate tie and nwell tie in a standard cell.
As the others reply you need to go back or...
0.13um cmos
Hi,
1) I suppose you have LVS problem with your nfet. Could you explain what is this problem?
2) Is this mos come with a deep nwell or anything like that (I mean in the layout)?
3) Did you try to LVS this nfet only in a test case cell?
4) Did you try to create a "flat tie" just by...
ibm subc
Hi,
I don't know the cmrf8sf technology but anyway for every technology you need PTAP to connect the B terminal of a NMOS.
What are "subc, nTiedown", type of contact?
When you choose your contact just make sure it's just active area, contact, m1 and of course P implant!!
Franck.
Re: Test Chip??
test of part of the production chip
test of prototype
test of a large range of devices as mos, bipolar, resistor, inductor, capacitor ...
test of memories
You should pad all those structures to be compliant with your probe station
Re: VLW window
The VLW contains all the layers used by Assura in the drc file. Look at this file and you'll understand.
It is usefull when you don't understand an error.
It is also usefull to create your own LVS or DRC file.
Franck.
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