Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by FPGAdevel

  1. F

    can the FPGA transmist the wireless data ?

    Re: wireless what kind of data ? where that get it ? what is transmitter ? what is reciever ?
  2. F

    VHDL Verilog synthesisible code using matlab

    VHDL Matlab Is it posible to make VHDL or Verilog synthesisible code using matlab ?
  3. F

    VERILOG: Fixed point library

    I wrote program for ACTEL FPGA using Libero IDE with verilog language. I was using in this program real variables that Synplify synthesiser not compiling. I need to substitute that kind of vars with vars defined thru reg or wire types.
  4. F

    VERILOG: Fixed point library

    Hi. I need to use fixed point numbers in my Verilog module and i looking for some special libraries for that. I have found one but its VHDL lib. Can you guys help me with that please.
See more

Part and Inventory Search

Back
Top