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Re: Divide By N counter
why vhdl to build a counter with dff "manually"!!!
in fact you should use the numeric_std library
and use these instructions:
process(raz,clk)
if raz='1' then qint <=(others=> '0');
elsif rising_edge(clk)
qint<= std_logic_vector(unstigned(dint)+1);
end if;
end...
Re: State Machines.
Are you sure of the good quality of your vhdl code? odes the xilinx synthesis tool recognize a state machine?
If not, rewrite the vhdl.
If yes, then you must find the critical path! to understand where the combinatory part has to be changed! this with timing analysis
You...
Re: DSP or FPGA/CPLD
in fact
fpga are for architecture developpers (hardware!)
and dsp for soft developpers!
it is not the same approach!
Aniway, NOW, embedded mac in fpga make them more efficient and powerfull than dsp!
also they can do // computation, (not possible in dsp)
BUT...
you...
I have a board with an ali M1535D+ chipset
I am looking for this chipset documentation.
(doc not available on ali's site)
OR any usefull information to program it...
thank you
mp3 decoder project in vhdl
Hello
first of all, congratulations for this design! nice work
I am a lecturer and i want my students to build part of this design in fpga xilinx!
So I am interested in your design! Have you tested it completely (with real music I mean!)
How many slices did you...
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