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Recent content by fpga-developer

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    High-Speed Digital Devices Design!

    We develop and manufacture electronic devices by order. We are the ones you should address when you need to produce and implement your own, unique device. We operate in strict accordance to the specification, therefore cooperation with us provides the exact result you expect. Using our services...
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    Stack-up of a six-layer help

    Hi! In my case pcb is high speed (single impedanse 50ohm, differential 100ohm), and routed signals on L1,L,L6 layers must have GND plane for robust signal integrity. In my opinion in your case pcb is high speed too. In my board there are 4 different powers and i route them on one layer (L4). I...
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    Stack-up of a six-layer help

    Hi! here is my sample. Via 0.5/0.2 [mm] minimal line width/clearance 0.1/0.1[mm] L1 – Signal L2 – GND L3 – Signal/Power L4 – Signal/Power L5 – GND L6 – Signal
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    [MOVED] 6 layer stack up, 50ohm - single, 100 ohm diff, low cost prototype suggestions

    [MOVED] 6 layer stack up, 50ohm - single, 100 ohm diff, low cost prototype suggestions Hi! Structure of my PCB stack up: L1--^---^--- SIG L2----------- GND [PLANE] L3--^---^--- SIG/PWR L4--^---^--- SIG/PWR L5----------- GND [PLANE] L6--^---^--- SIG on L1/L6 assembled BGA (DDR2,FPGA) with...
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    Verilog Instruction for finding absolute value!

    Re: verilog absolute value module abs( input [7:0] a, input [7:0] b, output [7:0] res ); wire [7:0] tmp; assign tmp = a-b; assign res = (~tmp[7:0])+8'h01; endmodule
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    AT91SAM9G45 DDR2, board_memories.c

    Good day, friends! I create PCB with at91sam9g45 + DDR2 (multiport) chip - MT47H32M16. I can't work with this DDR2. In standart library file board_memory.c i find some mistakes: Use config branch for DDR_SAMSUNG_M470T6554EZ3_CE6, in step 16 configure EMRS1 (write to addres *(pDdr+0x1000000) in...
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