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Just for more general knowledge...
I know as long as the current is higher on the source I'm good, but what about voltage? If voltage is lower/higher that means internal circuitry could burn out. Am I correct?
See the following specs and product:
Specification Current Voltage Power
USB 1.0 50 mA 5 V 0.75W
USB 2.0 500 mA 5 V 2.5 W
USB 3.0 900 mA 5 V 4.5 W
USB 3.1 2 A 5 V 10 W
USB 3.1 5 A...
Hey everyone,
I developed a verilog module and SVTB around it. While compiling, I get the following assertion that fires. Unfortunately I have no idea where to start looking to debug this. Looking at a .so file doesn't do much for a human, and I've googled around but feel like this is...
I have a question about the order in which code will execute.
1 task reset();
2 ##[1:5] my_io.cb.rst <= 1'b1;
3 ##1 my_io.cb.rst <= 1'b0;
4 my_io.cb.iValid <= 1'b1;
5 my_io.cb.iCommand <= `PUSH_CMD;
6 my_io.cb.iData <= DEAD_BEEF;
7 ##[1:2] my_io.cb.rst <= 1'b1;
8...
I want to take my question 1 step further. What if I want to add constraints?
Going back to my example, if I have a fifo and I want to randomize pushes, pops, and push_pops, however, I also want to ensure that I never pop when the fifo is empty?
I looked around online and found "constraint...
I am trying to learn SV on my own and came accross this piece of code:
task reset();
##1 fifo_io.cb.resetb <= 1'b1;
##1 fifo_io.cb.resetb <= 1'b0;
fifo_io.cb.in_vld <= 1'b0;
fifo_io.cb.out_rdy <= 1'b0;
##1 fifo_io.cb.resetb <= 1'b1;
repeat (2) @(fifo_io.cb);
endtask...
I am trying to test a simple fifo design and would like to call various tasks (push, pop, pushpop) randomly.
How can I do that?
I'm new to Verilog and SV so please bear that in mind in the explanation.
Thanks
I had searched through several online resources before posting this. It tells me to do it the way I had:
`define name value
`define MY_DELAY 2
`define PI 3.14
When I tried adding that character I got new errors:
Code:
`define `DATA_WIDTH 16
Error:
Error-[MMN] Missing macro name...
Not sure why I am getting this error. I've tried different things but haven't found the right solution.
Error-[IND] Identifier not declared
./rtl/fifo.v, 23
Identifier 'DATA_WIDTH' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to...
Can I have a sensitivity list for my always block as follows:
wire clk;
reg [100:0] myVector;
reg doStuff;
always @(posedge doStuff or myVector)
so that if any bits of myVector changes or if doStuff goes high the block executes.
That was very helpful. Thanks!
a) I didn't know you could vary clock frequencies. I can do that with verilog code? How do I define this clock?
I've heard of CDC (Clock Domain Crossing) but I thought those were physical clocks. So when people discuss CDC are they referring to clocks defined...
Well your jumping ahead - I've figured out the priority part and once it's in the queue I'm good.
For my design, priority is set by id number, since when looking at the dedicated request lines I will loop through the client lines. And yes I am using a queue to serve the requests. However, my...
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