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Recent content by floatice

  1. F

    cmos Voltage Step down/Step up detecting circuit in IC

    you can use bulk structure for voltage down and booster for voltage up
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    negative voltage generator

    generate a negative veference voltage,then use a regulator.
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    How important is SPICE today and how will it be in the future?

    Is SPICE dead? Hspice is still a industral standrad verification tool for analog circuit!!
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    A problem in installing IC5033 on RHEL 5

    If you use IC5033,the Redhat AS3 is best!
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    what is the best books/papers on bandgap voltage reference?

    I feel "Cmos Circuit design and layout" by jacob Baker is suit for you, it is easy and good theorectical understanding.
  6. F

    Redhat8 boot error: duplicate/badd block in inode 1434902.

    when i want to boot my Redhat8 system,he tell me that my linux do not shutdown cleanly, then screen display some message: duplicate/badd block in inode 1434902. then i can not enter it,when i use the command "fsck -a" to repair it,it do not works. How can i do??
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    IC layout design software

    you can choose IC layout tool (Tanner) in windowons platform.
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    Analog and Digital Design

    Absolutely analog design!!
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    How to deal with the high input voltage of LDO

    Pmos transistor you choose must be 5v tolerance transistor.Thought the process is 0.18um, the 5v tolerance transistor can sustain the gate drain or source voltage of 5v.
  10. F

    How to get rid of schematic annotation in Cadence schematic?

    you need to write a skill program,then load it. Added after 4 minutes: the skill language example: alias bk hiSetBindKey bk("Schematics" "Alt<Key>9" "geDeleteNetProbe()") bk("Symbol" "Alt<Key>9" "geDeleteNetProbe()") unalias bk
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    What companies are looking for freshers in VLSI??

    vlsi job help make more projects is good!!
  12. F

    Mounting NTFS Drives on Linux

    It depends on the your linux OS verision.
  13. F

    How to simulate ESD protection circuit?

    you can get help from the book "ESD in Silicon Integrated Circuits".
  14. F

    cadence - Virtuoso Schematic Composer - flip a transistor

    cadence layout move flip when copy a instance, enter F3 then you will select to flip it.
  15. F

    CMOS logic gates and digital circuits in 0.18u process

    logic gate design using 0.18u technology The W and L of logic circuit is the function of Speed and the load.You can get them by carefully simulation.
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