Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by flesher

  1. F

    how to control the delta sigma modulator for SSCG

    Hi, All, I am working on the SSCG, some question for you. Normally, there are two type of sscg . one is to modulate the vco control voltage . another is to modulate the divider ratio. Using the delta sigma modulator is the common way to control divider. But how to control the delta sigma...
  2. F

    how to design smooth swithing from CC mode to CV mode for battery charger?

    Hi, I am trying to design a Li ion battery charger. after reading some datasheet, I found that the smooth switching from constant current mode to constant voltage is critical point. I found that implementation in LTC4062 is quite interesting. here I have some question about it 1), why the bulk...
  3. F

    damping factor and Phase margin in PLL

    In the second order control systerm Hclosd(s)=Wn^2/(S^2+2EWnS+Wn^2), where E=damping factor. Normally, the larger damping factor, the more stable for the systerm. In third order type II PLL, Hcolsed(s)=Wn^2(1+S/Wz)/(S^2+2EWnS+Wn^2), Here: Natural Freq: Wn=sqrt[(Kvco*Icp)/(2*pi*Cbig*N)]...
  4. F

    how to design SHA for pipeline ADC ?

    thank you sutapanaki. You did help me a lot.
  5. F

    how to design SHA for pipeline ADC ?

    Hello guys, some question about pipeline ADC Front end SHA? 1, what's the capacitor mismatch requirement ? I found that many thesis say ΔC/C< 1 LSB, why it isn't 0.5 LSB? If the ADC resolution is N, ΔC/C<1/2^(N+1) or 1/2^N? 2, how to do the AC simulation for the OTA used in SHA? I know ,for...
  6. F

    what's the advantage of PLL compared with DLL?

    Hi, If I need 20 phases clock whose frequency are same with input clock(165MHz). Do I need a PLL or DLL? thank you?
  7. F

    how to decide LDO's bandwidth used for VCO

    Hello, a LDO is used for VCO, for example if VCO's frequency range is 120MHz~330 MHz, how to pick up the bandewidth for LDO? Thank you in advance.
  8. F

    what simulation need to do for pipeline ADC?

    Hi, I am a new pipeline ADC designer. what's the design procedure? and what simulation need to do ? For example, a 100M 10bit pipeline ADC? Thank you in advance.
  9. F

    PLL Bandwidth definition and calculation?

    pll bandwidth 1, When designing PLL, it is always said that PLL's bandwidth should be set to be smaller than Fref/10. what's the PLL bandwidth? Is it Wc(open loop unit gain bandwidth), Wn( Natural frequency) or W-3db ( closed loop -3db frequency)? 2, and I know Wc means the frequency where...
  10. F

    PLL bandwidth - Is it Wc, Wn or W-3db ? the formulars ?

    pll bandwidth 1, When designing PLL, it is always said that PLL's bandwidth should be set to be smaller than Fref/10. what's the PLL bandwidth? Is it Wc(open loop unit gain bandwidth), Wn( Natural frequency) or W-3db ( closed loop -3db frequency)? 2, and I know Wc means the frequency where...

Part and Inventory Search

Back
Top