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Recent content by flanix

  1. F

    VHDL synthesis problem - number of I/O bound exceeds

    VHDL synthesis problem will you delet the unused IO
  2. F

    VHDL Problem, please some help, it's just a division

    sure if i konw, i can give you a favour. give a email address. i will give you some useful information.
  3. F

    VHDL: converting 64bit vector to 32bit vector

    you can try this: add signal signal temp : signed(63 downto 0); temp(31 downto 0) <= "00000000000000000000000000001111" foo <= res + temp;
  4. F

    VHDL Problem, please some help, it's just a division

    you can use 'case statement' and subtration.
  5. F

    LCD monitor Service Manuals

    lcd monitor service manual i need too thank you
  6. F

    I need a transceiver IC for USART that converts 3v to 5v output and 5v to 3v input

    converting 5v uart to 3.3 v you can use resistance net
  7. F

    How can I describe a ROM in VHDL?

    dds vhdls you can use quartus LMP ROM, it very easy. if you cann't do it yourself, tell me>
  8. F

    any provision of signal attributes in verilog ?

    verilog... that is right!
  9. F

    read/write from dual port ram?

    hardware dual ram read / write you can use the memery on FPGA.
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