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The picture shows an one-port oscillator. I am having trouble proving that when Rp is bigger than 2/gm, the magnitude of the loop gain will be bigger than 1. Basically, I am trying to see if the one-port oscillator fit into barkhausen criterion. I can prove the phase of this circuit is 0 but the...
When using relaxation time approximation (RTA) on Boltzman Transport Equation (BTE), is it appropriate to use high temperature approximation(HTA)? if so, why?
Re: Capacitor Mismatch
Thank you for the replying...
Does anyone know what is the unit capacitance of a 12 bit successive approximation ADC?
Are the capacitors that people use in a 12 bit SA-ADC the same as
the ones they use in pipeline ADC?
Re: Capacitor Mismatch
Raj, thank you for the reply.
However, the answer that I am looking for is not the causes of the mismatch but rather the value of the mismatch. For example, small capacitors are hard to match with each other. Let C be the unit capacitance and say I want a ratio 1:1...
I have one question regarding the sample and hold amplifier in the picture.
During phase 1, SH(1), S1, Seq, and S2 are all closed and S3 is open. During this time, Vx and Vy are equal to the offset voltage of the opamp.
During phase 2, SH(2), S2 opens and injects some charge onto the node Vx...
sar capacitor mismatch
I have been trying find some information on what cause capacitor mismatch,
so far the only thing that I know is that there is a random edge variation. Other possible causes such as undercut, long range gradients. They all can be eliminated using common centroid geometry...
everytime I simulate my circuit, it always says that PARAMETER HAS NOT BEEN SET: spectre, does anyone know how to solve this problem? thx
The simulator I am using is spectreS and I get this error only when I use spectreS. If I use other simulators, for example, spectre, then I dont get this...
differential to single end comparator
thx for the reply, but if you can, show me your hand analysis and prove me wrong. cuz i dont think i made a mistake...and i believe spice didnt either...
singal end vs fully differential
Fvm
Actually, I just did a hand analysis and I found out that the circuit you have posted would not integrate at all. but thx for replying anyway...
ok so for the power supply of an ADC most of them are 3.3 and 1.8V. but why? why not 1.9V? why not 2.0V? why 1.8V? i dont understand.
I am trying to design a comparator for SA-ADC. if my Vdd is 1.8V and Vss = 0 = gnd, how is the minimum input common mode range be enough? I mean I need something...
I am having trouble simulating circuits in cadence spectre virtuoso. Everytime the simulator gets to the "generating netlist", all the cadence spectre virtuoso windows would close and I would get a "segmentation fault" in the command window. Anyone know how to fix this problem?
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