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Thanks again, I have a huge binary text file with all the data inside it of one signal, it has header + timestamp + messages of that particular signal, I will be developing a C++ code for reading this file and converting it into VCD format. The data which I have is not from simulation but is...
Thanks for your reply, well this can also be done in Verilog using #define, but I mean to say that instead of wave forms (1' & 0's) Is there any possibility that I can display the NAME of a particular SEQUENCE lets say 1010101 as LNA message and 0101111 as Info message...in the display...
Is any one aware that there is any simulation tool which can take in any VCD file or any other format waveform file and display the waveforms as a pre-defined value for a particular pattern of data.
Suppose, I have a message consisting of Header + body, then instead of displaying the binary...
Well, I am not using JTAG to access the FPGA, I am using USB micro controller, that is the issue, It does have JTAG pins on the connector board but my project is being implemented and controlled entirely by software application....
I am working on an Design IP implemented on an FPGA, and to debug the outputs or inputs I have to add more ports to the module or also get some register or wire outputs on the IO ports for debug. But changing every time the modules(go through 5-6 hierarchy ) and again synthesizing the design and...
Well I did solved it, just using the concept of state machines, I used a write state machine(40Mhz) which depends on the existing state machine (40Mhz)which filters the Headers, Messages and CRC's, this writes data sequentially into the memory then I read the data back from the memory using read...
I am working on a de-serial module, and I have to collect information into a single register containing Header + Message + CRC. I am receiving serial data which will bean header of 8 bits and depending on my header bit there is a decoder which decides the length of each message and if CRC is...
Hello Everyone,
My project has a requirement for an FPGA Board. We have a design IP which generates data which we want to store in memory and further stream it through an USB or stream it directly through an USB onto a PC. Also, we require software API’s along with the board which enables to...
Hello Everyone, Well I am using Allegro PCB SI tool for simulating Micron's DDR2 to PowerPC using their IBIS model. I am comfortable with the tool and I understand the protocol for DDR2 but am unable to figure out the topology ie the connections, the terminations and their respective values...
Can I translate IBIS models on Hyperlynx SI, I have translated models on Signal Explorer, Cadence. I did check that Hyperlynx has an IBIS editor, but I want to add the models, topology from a manufacture's website, like IBIS DDR2 Ram from Micron. Please guide me.
If you want to change the logic voltage levels to communicate to the system then you can make a level shifter using max 232 IC. Check this out
Serial level converter (RS232-2-TTL converter) « benybee
I have to add 8 MB serial flash to my ARM 7 development board, I have done the physical connections and my objective is to write data into the flash through port D or C, But I want to know to which address do I need to store this particular program to the flash?
Please guide.....
I am trying to complie my design on Synopsys DC but I get the following error:
Error: Could not read the following target libraries:
class.db and_or.db
(UIO-3)
0
Is there some problem with the environment settings?
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